MAX32665-MAX32668 User Guide
Maxim Integrated Page 352 of 457
corresponding pulse train engine is already enabled and running, writing a 1 to that bit position in the PTG_SAFE_EN
register has no effect.
17.5.2 Pulse Train Atomic Disable
PTG_SAFE_DIS “Global Safe Disable” is a write-only register for disabling a pulse train engine without performing a RMW.
To safely disable pulse train engines, write a 32-bit value to this register with a 1 in the bit positions corresponding to the
pulse train engines to be disabled. This immediately clears to 0 the corresponding bits in PTG_ENABLE which disables the
corresponding pulse train engines. Writing a 0 to any bit position in the PTG_SAFE_DIS register has no effect on the state of
the corresponding pulse train enable bit.
Bit banding is not supported for the PTG_ENABLE, PTG_SAFE_EN, and PTG_SAFE_DIS registers and can have unpredictable
results.
17.6 Pulse Train Halt and Disable
Once a pulse train engine is enabled and running, it continues to run until one of the following events stops the output:
The corresponding enable bit in the PTG_ENABLE register is cleared to 0 to halt the output.
A 1 is written to the corresponding disable bit in the PTG_SAFE_DIS register to halt the output.
The corresponding resync bit in the PTG_RESYNC register is cleared to 0 to halt and reset the output.
PTn_LOOP was initialized to a non-zero value, and the loop count has reached 0 (this has no effect in Square Wave mode; it
only applies to pulse train mode).
When a pulse train is halted, the corresponding enable bit in PTG_ENABLE is automatically cleared to 0.
17.7 Pulse Train Interrupts
Each pulse train can generate an interrupt only if it is configured in pulse train mode, and the loop counter PTG_SAFE_DIS
was initialized to a non-zero number. When PTG_SAFE_DIS counts down to 0, the corresponding status flag in the
PTG_INTFL register is set. If the corresponding interrupt enable bit in the PTG_INTEN register is set, the event also
generates an interrupt.
17.8 Registers
See Table 3-1: APB Peripheral Base Address Map for this peripheral/module's base address. If multiple instances are
provided, each will have a unique base address. Unless specified otherwise, all fields are reset on a system reset, soft reset,
POR, and the peripheral-specific reset, if applicable.
Table 17-1: Pulse Train Engine Register Summary
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