Maxim Integrated MAX32665 - Table 8-17. SPIXFM Fetch Control Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 163 of 457
SPIXFM Configuration Register
SPIXFM_CFG
[0x0000]
Bits
Name
Access
Reset
Description
17:16
ssact
R/W
0
Slave Select Active Timing
Controls delay from assertion of slave select to start of the SCK pulse and delay
from the end of SCK pulses to de-assertion of slave select. See 8.2.1.1.6, above,
for details on slave select transaction delay configuration.
0b00: 0 system clocks
0b01: 2 system clocks
0b10: 4 system clocks
0b11: 8 system clocks
15:12
hiclk
R/W
0
SCK High Clocks
Number of system clocks that SCK is held high when SCK pulses are generated.
0: Invalid
All other values: The number of system clocks that SCK is held high.
11:8
loclk
R/W
0
SCK Low Clocks
Number of system clocks that SCK is held low when SCK pulses are generated.
0: Invalid
All other values: The number of system clocks that SCK is held low.
7
-
R/W
0
Reserved for Future Use
Do not modify this field.
6:4
ssel
R/W
0
Slave Select
Only valid value is zero
3
-
R/W
0
Reserved for Future Use
Do not modify this field.
2
sspol
R/W
1
Slave Select Polarity
This bit controls the polarity of the slave select.
0: Slave Select active high
1: Slave Select active low
1:0
mode
R/W
0
SPI mode
Set this field to the required SPI mode.
0b00: SPI mode 0
0b01: Reserved
0b10: Reserved
0b11: SPI mode 3
Table 8-17. SPIXFM Fetch Control Register
SPIXFM Fetch Control Register
SPIXFM_FETCH_CTRL
[0x0004]
Bits
Name
Access
Reset
Description
31:17
-
R/W
0
Reserved for Future Use
Do not modify this field.
16
addr4
R/W
0
Four-Byte Address mode
Enables 4-byte Flash Address mode. Defaults to value as defined by parameter
in instantiation. User can override.
0: 3-byte address mode
1: 4-byte address mode