MAX32665-MAX32668 User Guide
Maxim Integrated Page 289 of 457
During a receive transaction (which during master operation is a READ, and during slave operation is a WRITE), received
bytes are automatically written to the RX FIFO. Software should monitor the RX FIFO level and unload data from it as
needed by reading I2Cn_FIFO. If the receive FIFO becomes full during a master mode transaction, then the controller sets
the I2Cn_INT_FL1.rxofi the I2Cn_INT_FL1.rxofi bit and one of two things will happen depending on the value of
I2Cn_CTRL0.scl_strd:
• If clock stretching is enabled (I2Cn_CTRL0.scl_strd = 0), then the controller stretches the clock until software makes
space available in the RX FIFO by reading from I2Cn_FIFO. Once space is available, the peripheral moves the data
byte from the shift register into the RX FIFO, the SCL device pin is released, and the master is free to continue the
transaction.
• If clock stretching is disabled (I2Cn_CTRL0.scl_strd = 1), then the controller responds to the master with a NACK
and the data byte is lost. The master can return the bus to idle with a STOP condition or start a new transaction
with a RESTART condition.
During a transmit transaction (which during master operation is a WRITE, and during slave operation is a READ), either user
software or the DMA can provide data to be transmitted by writing to the TX FIFO. Once the peripheral finishes transmitting
each byte, it removes it from the TX FIFO and, if available, begins transmitting the next byte.
Interrupts can be generated for the following FIFO status:
• TX FIFO level less than or equal to threshold
• RX FIFO level greater than or equal to threshold
• TX FIFO underflow
• RX FIFO overflow
• TX FIFO locked for writing
Both the RX FIFO and TX FIFO are flushed when the I
2
C port is disabled by clearing I2Cn_CTRL0.i2cen=0. While the
peripheral is disabled, writes to the TX FIFO have no effect and reads from the RX FIFO return 0xFF.
The TX FIFO and RX FIFO can be flushed by setting the Transmit FIFO Flush bit (I2Cn_TX_CTRL0.txfsh=1) or the Receive FIFO
Flush bit (I2Cn_RX_CTRL0.rxfsh=1), respectively. In addition, under certain conditions the TX FIFO is automatically locked by
hardware and flushed so stale data is not unintentionally transmitted. The TX FIFO is automatically flushed, and writes
locked out from software under the following conditions:
• General Call Address Match. Automatic flushing and lockout can be disabled by setting
I2Cn_TX_CTRL0.gcamtxafdis.
• Slave Address Match Write. Automatic flushing and lockout can be disabled by setting
I2Cn_TX_CTRL0.samwtxafdis.
• Slave Address Match Read. Automatic flushing and lockout can be disabled by setting I2Cn_TX_CTRL0.samrtxafdis.
• During operation as a slave transmitter, a NACK is received. Automatic flushing and lockout can be disabled by
setting I2Cn_TX_CTRL0.rnacktxafdis.
• Any of the following interrupts: Arbitration Error, Timeout Error, Master Mode Address NACK Error, Master Mode
Data NACK Error, Start Error, and STOP Error. Automatic flushing cannot be disabled for these conditions.
When the above conditions occur, the TX FIFO is flushed so that data intended for a previous transaction is not
unintentionally transmitted for a new transaction. In addition to flushing the the TX FIFO, the Transmit Lockout Flag is set
(I2Cn_INT_FL0.txloi=1) and writes to the TX FIFO are ignored until firmware acknowledges the external event by clearing
I2Cn_INT_FL0.txloi.
13.4.10 TX FIFO Preloading
There may be situations during slave mode operation where software wants to preload the TX FIFO prior to a transmission,
such as when clock stretching is disabled. In this scenario, rather than responding to an external master requesting data
with an ACK and clock stretching while software writes the data to the TX FIFO, the controller will instead respond with a
NACK until software has preloaded the requested data into the TX FIFO.
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