Maxim Integrated MAX32665 - Figure 4-4: DEEPSLEEP Clock Control

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MAX32665-MAX32668 User Guide

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Figure 4-4: DEEPSLEEP Clock Control

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Default Chapter2
- Table of Contents2
1 Overview24
- Block Diagram25
- Figure 1-1: MAX32665-MAX32668 Block Diagram25
2 Resource Protection Unit (RPU)26
- Instances26
- Table 2-1: Dual Mapped APB Peripherals26
- Table 2-2. MAX32665-MAX32668 Master Permission Bits26
- Table 2-3: MAX32665-MAX32668 AHB Slaves27
- Table 2-4. MAX32665-MAX32668 AHB Master/Slave Interconnect Matrix27
- Usage28
- Registers29
- Table 2-5: RPU APB Register Offsets, Names, Access, and Descriptions29
- Table 2-6: RPU AHB Slave Register Addresses, Names, Access, and Descriptions30
- Register Details31
- Table 2-7: RPU APB Slave Permission Registers31
- Table 2-8: RPU AHB Slave Permission Register33
3 Memory, Register Mapping, and Access34
- Memory, Register Mapping, and Access Overview34
- Figure 3-1: Code Memory Mapping35
- Figure 3-2: Data Memory Mapping36
- Standard Memory Regions37
- Device Memory Instances39
- AHB Interfaces40
  - Core AHB Interfaces40
  - AHB Masters41
- Peripheral Register Map41
- Error Correction Coding (ECC) Module43
4 System, Power, Clocks, Reset50
- Oscillator Sources and Clock Switching50
  - Figure 4-1: Clock Block Diagram51
  - 32Mhz Bluetooth Radio Oscillator52
  - 60Mhz Low Power Internal Oscillator52
  - 96Mhz Internal Main High-Speed Oscillator52
  - Oscillator Inplementation52
  - 8Khz Ultra-Low Power Nano-Ring Internal Oscillator53
  - 8Mhz Internal Oscillator53
  - Figure 4-2: Example 32Mhz Crystal Capacitor Determination53
  - Khz External Crystal Oscillator53
- Operating Modes54
  - ACTIVE Mode54
  - SLEEP Low Power Mode54
  - Table 4-1: Wakeup Sources54
  - Figure 4-3: SLEEP Mode Clock Control55
  - DEEPSLEEP Low Power Mode56
  - Figure 4-4: DEEPSLEEP Clock Control57
  - BACKUP Low Power Mode58
  - Figure 4-5: BACKUP Mode Clock Control59
- Device Resets60
  - Table 4-2: Reset and Low Power Mode Effects60
  - Peripheral Reset61
  - Soft Reset61
  - Power-On Reset62
  - System Reset62
- Cache62
- Instruction Cache Controller63
  - Enabling ICC0/ICC1/SFCC63
  - Figure 4-6: MAX32665-MAX32668 Cache Controllers Control63
  - Flushing the ICC0/ICC1/SFCC Cache64
  - Flushing SRCC Cache64
- Instruction Cache Controller Registers64
- Table 4-3: Instruction Cache Controller Register Summary64
- Table 4-4: SPIXF Cache Controller Register Summary64
- Table 4-5: Iccn Cache ID Register64
- Table 4-6: Iccn Memory Size Register65
- Table 4-7: Iccn Cache Control Register65
- Table 4-8: Iccn Invalidate Register65
- Table 4-9: SFCC Cache ID Register65
- External RAM SPIXR Cache Controller (SRCC)66
- Table 4-10: SFCC Memory Size Register66
- Table 4-11: SFCC Cache Control Register66
- Table 4-12: SFCC Invalidate Register66
- RAM Memory Management67
  - RAM Zeroization67
  - RAM Low Power Modes67
  - Table 4-13 RAM Block Size and Base Address67
- Miscellaneous Control Registers68
- Miscellaneous Control Registers Details68
- Table 4-14 Miscellaneous Control Register Summary68
- Table 4-15: Error Correction Coding (ECC) Enable Register68
- Table 4-16: SQWOUT and PDOWN Output Enable Register69
- Table 4-17: Comparator Enable Register69
- Table 4-18: Control Register70
- Single Inductor Multiple Output (SIMO) Power Supply71
  - Power Supply Monitor71
  - Table 4-19: SIMO Power Supply Device Pin Connectivity71
- Single Inductor Multiple Output (SIMO) Registers72
- Table 4-20: SIMO Controller Register Summary72
- Single Inductor Multiple Output (SIMO) Registers Details73
- Table 4-21: Buck Voltage Regulator a Control Register73
- Table 4-22: Buck Voltage Regulator B Control Register73
- Table 4-23: Buck Voltage Regulator C Control Register74
- Table 4-24: Buck Voltage Regulator D Control Register74
- Table 4-25: High Side FET Peak Current VREGO_A VREGO_B Register74
- Table 4-26: High Side FET Peak Current VREGO_C VREGO_D Register75
- Table 4-27: Maximum High Side FET Time on Register75
- Table 4-28: Buck Cycle Count VREGO_A Register75
- Table 4-29: Buck Cycle Count VREGO_B Register75
- Table 4-30: Buck Cycle Count VREGO_C Register76
- Table 4-31: Buck Cycle Count VREGO_D Register76
- Table 4-32: Buck Cycle Count Alert VREGO_A Register76
- Table 4-33: Buck Cycle Count Alert VREGO_B Register76
- Table 4-34: Buck Cycle Count Alert VREGO_C Register76
- Table 4-35: Buck Cycle Count Alert VREGO_D Register77
- Table 4-36: Buck Regulator Output Ready Register77
- Table 4-37: Zero Cross Calibration VREGO_A Register77
- Power Sequencer and Always-On Domain Registers78
- Table 4-38: Zero Cross Calibration VREGO_B Register78
- Table 4-39: Zero Cross Calibration VREGO_C Register78
- Table 4-40: Zero Cross Calibration VREGO_D Register78
- Table 4-41: Power Sequencer and Always-On Domain Register Summary78
- Power Sequencer and Always-On Domain Register Details79
- Table 4-42: Low Power Control Register79
- Table 4-43: GPIO0 Low Power Wakeup Status Flags80
- Table 4-44: GPIO0 Low Power Wakeup Enable Registers80
- Table 4-45: GPIO1 Low Power Wakeup Status Flags80
- Table 4-46: GPIO1 Low Power Wakeup Enable Registers80
- Table 4-47: Peripheral Low Power Wakeup Status Flags81
- Table 4-48: Peripheral Low Power Wakeup Enable Register82
- Table 4-49: RAM Shutdown Control Register83
- Table 4-50: Low Power VDD Power down Register84
- Global Control Registers (GCR)85
- Table 4-51: BACKUP Return Vector Register85
- Table 4-52: BACKUP Aod Register85
- Table 4-53: Global Control Register Summary85
- Global Control Register Details (GCR)86
- Table 4-54: System Control Register86
- Table 4-55: Reset Register 087
- Table 4-56: System Clock Control Register90
- Table 4-57: Power Management Register92
- Table 4-58: Peripheral Clock Divisor Register93
- Table 4-59: Peripheral Clock Disable Register 094
- Table 4-60: Memory Clock Control Register96
- Table 4-61: Memory Zeroization Control Register98
- Table 4-62: System Status Flag Register100
- Table 4-63: Reset Register 1100
- Table 4-64: Peripheral Clock Disable Register 1102
- Table 4-65: Event Enable Register105
- Table 4-66: Revision Register106
- Table 4-67: System Status Interrupt Enable Register106
- Table 4-68: Error Correction Coding Error Register106
- Table 4-69: Error Correction Not Double Error Detected Register107
- Table 4-70: Error Correction Coding Interrupt Enable Register109
- Table 4-71: Error Correction Coding Address Register110
- Table 4-72: Bluetooth LDO Control Register110
- Table 4-73: Bluetooth LDO Delay Count Register112
- Table 4-74: General Purpose 0 Register112
- Table 4-75: Arm Peripheral Bus Asynchronous Bridge Select Register112
- Function Control Registers113
- Function Control Register Details113
- Table 4-76: Function Control Register Summary113
- Table 4-77: Function Control Register 0113
- AES Key Registers114
- AES Key Register Details114
- Table 4-78: AES Key Register Summary114
- Table 4-79: AES Key 0 and 1 Registers114
- Table 4-80: AES Key 2 and 3 Registers114
5 Interrupts and Exceptions115
- Features115
- Interrupt Vector Table115
- Table 5-1: MAX32665-MAX32668 Interrupt Vector Table115
6 General-Purpose I/O and Alternate Function Pins (GPIO)119
- Instances119
- Table 6-1: MAX32665-MAX32668 GPIO Pin Count119
- Table 6-2: MAX32665-MAX32668 GPIO and Alternate Function Matrix, 140 WLP120
- Table 6-3: MAX32665-MAX32668 GPIO Pin Configuration121
- Table 6-4: MAX32665-MAX32668 Input Mode Configuration121
- Table 6-5: MAX32665-MAX32668 Output Mode Configuration122
- Table 6-6: MAX32665-MAX32668 GPIO Port Interrupt Vector Mapping122
- Usage123
  - Reset State123
  - Input Mode Configuration123
  - Output Mode Configuration123
  - Alternate Function Configuration123
- Configuring GPIO (External) Interrupts123
  - GPIO Interrupt Handling124
  - Using GPIO for Wakeup from Low Power Modes124
  - Table 6-7: MAX32665-MAX32668 GPIO Wakeup Interrupt Vector124
- Registers125
- Table 6-8: GPIO Register Summary125
- Register Details126
- Table 6-9: GPIO Port N Configuration Enable Bit 0 Register126
- Table 6-10: GPIO Port N Configuration Enable Atomic Set Bit 0 Register126
- Table 6-11: GPIO Port N Configuration Enable Atomic Set Bit 0 Register126
- Table 6-12: GPIO Port N Output Enable Register126
- Table 6-13: GPIO Port N Output Enable Atomic Set Register127
- Table 6-14: GPIO Port N Output Enable Atomic Clear Register127
- Table 6-15: GPIO Port N Output Register127
- Table 6-16: GPIO Port N Output Atomic Set Register127
- Table 6-17: GPIO Port N Output Atomic Clear Register127
- Table 6-18: GPIO Port N Input Register128
- Table 6-19: GPIO Port N Interrupt Mode Register128
- Table 6-20: GPIO Port N Interrupt Polarity Register128
- Table 6-21: GPIO Port N Input Enable Register128
- Table 6-22: GPIO Port N Interrupt Enable Register129
- Table 6-23: GPIO Port N Interrupt Enable Atomic Set Register129
- Table 6-24: GPIO Port N Interrupt Enable Atomic Clear Register129
- Table 6-25: GPIO Port N Interrupt Status Register129
- Table 6-26: GPIO Port N Interrupt Clear Register129
- Table 6-27: GPIO Port N Wakeup Enable Register130
- Table 6-28: GPIO Port N Wakeup Enable Atomic Set Register130
- Table 6-29: GPIO Port N Wakeup Enable Clear Register130
- Table 6-30: GPIO Port N Interrupt Dual Edge Mode Register130
- Table 6-31: GPIO Port N Pullup Pulldown Selection 0 Register130
- Table 6-32: GPIO Port N Pullup Pulldown Selection 1 Register131
- Table 6-33: GPIO Port N Configuration Enable Bit 1 Register131
- Table 6-34: GPIO Port N Configuration Enable Atomic Set, Bit 1 Register131
- Table 6-35: GPIO Port N Configuration Enable Atomic Clear, Bit 1 Register131
- Table 6-36: GPIO Port N Configuration Enable Bit 2 Register132
- Table 6-37: GPIO Port N Configuration Enable Atomic Set Bit 2 Register132
- Table 6-38: GPIO Port N Configuration Enable Atomic Clear Bit 2 Register132
- Table 6-39: GPIO Port N Output Drive Strength Bit 0 Register132
- Table 6-40: GPIO Port N Output Drive Strength Bit 0 Register132
- Table 6-41: Gpion Pulldown/Pullup Strength Select Register133
- Table 6-42: Gpion Supply Voltage Select Register133
7 Flash Controller (FLC)134
- Instances134
- Usage134
- Flash Error Correction Coding137
- Flash Controller Registers137
- Table 7-3: Flash Controller Registers137
- Flash Controller Register Details138
- Table 7-4: Flash Controller Address Pointer Register138
- Table 7-5: Flash Controller Clock Divisor Register138
- Table 7-6: Flash Controller Control Register138
- Table 7-7: Flash Controller Interrupt Register139
- Table 7-8: Flash Controller ECC Data Register140
- Table 7-9: Flash Controller Data Register 0140
- Table 7-10: Flash Controller Data Register 1140
- Table 7-11: Flash Controller Data Register 2140
- Table 7-12: Flash Controller Data Register 3141
8 External Memory142
- Overview142
- SPI Execute-In-Place Flash (SPIXF)142
- SPI Execute-In-Place RAM (SPIXR)167
- SPIXR Cache Controller (SRCC)178
- Secure Digital Host Controller181
9 Standard DMA (DMAC)222
- Instances222
- DMA Channel Operation (DMACH)223
  - DMA Channel Arbitration and DMA Bursts223
  - Table 9-1: MAX32665-MAX32668 DMAC and Channel Instances223
  - DMA Source and Destination Addressing224
  - Table 9-2: MAX32665-MAX32668 DMAC Source and Destination by Peripheral224
  - Data Movement from Source to DMA226
  - Data Movement from the DMA to Destination226
  - Table 9-3: Data Movement from Source to DMA FIFO226
  - Table 9-4: Data Movement from the DMA FIFO to Destination226
- Usage227
- Count-To-Zero (CTZ) Condition227
- Chaining Buffers228
- Figure 9-1: DMA Block-Chaining Flowchart229
- DMA Interrupts230
- Channel Timeout Detect230
- Table 9-5: DMA Channel Timeout Configuration230
- Memory-To-Memory DMA231
- DMAC Registers231
- DMAC Register Details231
- Table 9-6: DMAC Register Summary231
- Table 9-7: Dmacn Control Register231
- DMA Channel Registers232
- DMAC Channel Registers232
- Table 9-8: Dmacn Interrupt Register232
- Table 9-9: Standard DMA Channel 0 to Channel 7 Register Summary232
- Table 9-10: DMACH Channel Registers Summary232
- DMA Channel Register Details233
- Table 9-11: Dmachn Configuration Register233
- Table 9-12: DMA Status Register234
- Table 9-13: Dmachn Source Register235
- Table 9-14: DMA Channel N Destination Register236
- Table 9-15: DMA Channel N Count Register236
- Table 9-16: DMA Channel N Source Reload Register236
- Table 9-17: DMA Channel N Destination Reload Register236
- Table 9-18: DMA Channel N Count Reload Register237
10 Cyclic Redundancy Check Engine (CRC)238
- Instances239
- Linear Feedback Shift Register (LFSR)239
- Table 10-1: Common CRC Polynomials239
- Registers240
- Figure 10-1: Galois Field CRC and LFSR Architecture240
- Table 10-2: CRC Register Summary240
- Register Details241
- Table 10-3: CRC Control Register243
- Table 10-4: CRC DMA Source Register243
- Table 10-5: CRC DMA Destination Register243
- Table 10-6: CRC DMA Count Register243
- Table 10-7: CRC Data Input Registers244
- Table 10-8: CRC Data Output Registers244
- Table 10-9: CRC Polynomial Register244
- Table 10-10: CRC Value Register245
- Table 10-11: CRC Pseudo-Random Number Generator Register245
11 Analog to Digital Converter and Comparators (ADC)246
- Features246
- Instances246
- Table 11-1: MAX32665-MAX32668 ADC Peripheral Pins246
- Architecture247
- Figure 11-1: Analog to Digital Converter Block Diagram248
- Clock Configuration249
- Table 11-2: ADC Clock Frequency and ADC Conversion Time (&#Xd835;&#Xdc53;&#Xd835;&#Xdc46;&#Xd835;&#Xdc4C;&#Xd835;&#Xdc46;&#Xd835;&#Xdc36;&#Xd835;&#Xdc3F;&#Xd835;&#Xdc3E; = 96&#Xd835;&#Xdc40;&#Xd835;&#Xdc3B;&#Xd835;&#Xdc67;, &#Xd835;&#Xdc53;&#Xd835;&#Xdc43249
- Power-Up Sequence250
- Conversion250
- Reference Scaling and Input Scaling250
- Comparator Operation254
- Registers255
- Register Details255
- Table 11-5. ADC Registers Summary255
- Table 11-6: ADC Control Register255
- Table 11-7: ADC Status Register257
- Table 11-8: ADC Data Register257
- Table 11-9: ADC Interrupt Control Register257
- Table 11-10: ADC Limit 0 to 3 Registers258
12 Uart260
- Instances260
- UART Frame260
- Figure 12-1: UART Frame Diagram260
- UART Interrupts261
- UART Baud Rate Clock Source261
- UART Baud Rate Calculation261
- Table 12-1: UART Interrupt Conditions261
- Table 12-2: Example Baud Rate Calculation Results, Target Bit Rate = 1.8Mbps262
- UART Configuration and Operation263
- Wakeup Time263
- Hardware Flow Control263
- Registers263
- Register Details264
- Table 12-3: UART Register Summary264
- Table 12-4: UART Control 0 Register264
- Table 12-5: UART Control 1 Register266
- Table 12-6: UART Status Register266
- Table 12-7: UART Interrupt Enable Register267
- Table 12-8: UART Interrupt Flags Register268
- Table 12-9: UART Rate Integer Register270
- Table 12-10: UART Baud Rate Decimal Register270
- Table 12-11: UART FIFO Register270
- Table 12-12: UART DMA Configuration Register270
- Table 12-13: UART Transmit FIFO Data Output Register271
1 I C Master/Slave Serial Communications Peripheral (I2C)272
- Figure 13-1: I C Block Diagram273
14 Quad Serial Peripheral Interface (SPI)306
- Figure 14-1: QSPI Block Diagram306
15 Htimer (HT)324
- Overview324
- Alarm Functions324
  - Long-Interval Alarm324
  - Short-Interval Alarm324
- Register Access Control325
- Registers326
- Register Details326
- Table 15-1. Htimer Registers Summary326
- Table 15-2: Htimer Long-Interval Counter Register326
- Table 15-3: Htimer Short-Interval Counter Register326
- Table 15-4: Htimer Long-Interval Alarm Register326
- Table 15-5: Htimer Short-Interval Alarm Register326
- Table 15-6: Htimer Control Register327
16 Timers329
- Features329
- Basic Operation329
- Timer Pin Functionality330
- One-Shot Mode (000B)330
- Continuous Mode (001B)331
- Counter Mode (010B)334
- PWM Mode (011B)336
  - PWM Mode Timer Period336
  - PWM Mode Configuration336
- Capture Mode (100B)338
- Compare Mode (101B)339
- Gated Mode (110B)342
- Capture/Compare Mode (111B)344
  - Capture/Compare Timer Period344
  - Capture/Compare Configuration344
- Timer Registers345
- Table 16-1: Timer Register Offset, Names, Access and Descriptions345
- Table 16-2: Timer Count Registers345
- Table 16-3: Timer Compare Registers345
- Table 16-4: Timer Interrupt Registers346
- Table 16-5: Timer Control Registers346
- Table 16-6: Timer Non-Overlapping Compare Registers348
17 Pulse Train Engine (PT)349
- Instances349
- Pulse Train Engine Features349
- Engine349
  - Pulse Train Output Modes350
- Enabling and Disabling a Pulse Train Output351
- Atomic Pulse Train Output Enable and Disable351
  - Pulse Train Atomic Enable351
  - Pulse Train Atomic Disable352
- Pulse Train Halt and Disable352
- Pulse Train Interrupts352
- Registers352
- Table 17-1: Pulse Train Engine Register Summary352
- Register Details354
18 Real-Time Clock (RTC)369
- Overview369
- Figure 18-1. MAX32665-MAX32668 RTC Block Diagram (12-Bit Sub-Second Counter)369
- Instances370
- Register Access Control370
- RTC Alarm Functions371
- RTC Calibration374
- Table 18-3. MAX32665-MAX32668 RTC Square Wave Output Configuration374
- Figure 18-4. Internal Implementation of Digital Trim, 4Khz375
- Registers376
- Register Details376
- Table 18-4. RTC Register Summary376
- Table 18-5. RTC Seconds Counter Register376
- Table 18-6. RTC Sub-Second Counter Register (12-Bit)376
- Table 18-7. RTC Time-Of-Day Alarm Register377
- Table 18-8. RTC Sub-Second Alarm Register377
- Table 18-9. RTC Control Register377
- Table 18-10. RTC 32Khz Oscillator Digital Trim Register379
- Table 18-11. RTC 32Khz Oscillator Control Register379
19 Watchdog Timer (WDT)380
- Features381
- Usage381
- Figure 19-1: Watchdog Timer Block Diagram381
- Interrupt and Reset Period Timeout Configuration382
- Timed Access Protection382
- Table 19-1: Watchdog Timer Interrupt Period Fsys_Clk = 96Mhz and Fpclk = 48Mhz382
- Enabling the Watchdog Timer383
  - Enable Sequence383
- Disabling the Watchdog Timer383
  - Manual Disable383
  - Automatic Disable383
- Resetting the Watchdog Timer383
  - Reset Sequence383
- Detection of a Watchdog Reset Event383
- Registers383
- Table 19-2: Watchdog Timer Register Offsets, Names and Descriptions383
- Register Details384
- Table 19-3: Watchdog Timer Control Register384
- Table 19-4: Watchdog Timer Reset Register386
20 Wire Master (OWM)387
- Instances387
- Pins and Configuration388
- 1-Wire Protocol389
- 1-Wire Operation396
  - Resetting the OWM396
- 1-Wire Data Reads396
  - Reading a Single Bit Value from the 1-Wire Bus396
  - Reading an 8-Bit Value from the 1-Wire Bus397
- Registers397
- Table 20-4: OWM Register Summary397
- Register Details398
- Table 20-5: OWM Configuration Register398
- Table 20-6: OWM Clock Divisor Register399
- Table 20-7: OWM Control/Status Register399
- Table 20-8: OWM Data Register400
- Table 20-9: OWM Interrupt Flag Register400
- Table 20-10: OWM Interrupt Enable Register401
21 USB 2.0 High-Speed (USBHS) Host Interface with PHY402
- Instances402
- USBHS Bus Signals403
- USBHS Device Endpoints403
- Table 21-1: USB Bus States Indicated by the Differential Pair (D+, D-)403
- USBHS Reset and Clock404
- USBHS SUSPEND Mode and RESUME States404
- Packet Size405
- Endpoint 0 Control Transactions405
  - Endpoint 0 Error Handling405
- Bulk Endpoints Operation and Options405
- Interrupt Endpoints407
  - Interrupt in Endpoints407
  - Interrupt out Endpoints407
- Isochronous Endpoints407
- USBHS Device Registers409
- Table 21-5: USBHS Device Register Offsets, Names, Access, and Descriptions409
- USBHS Device Register Details410
22 Bluetooth 5 Low Energy (LE) Radio426
- Power-Efficient Design426
- Bluetooth Hardware Accelerator426
- Arm Cordio®-B50 Software Stack426
- Figure 22-1: MAX32665-MAX32668 Bluetooth Stack Overview427
- Pins428
- Configuration428
- Documentation428
23 Trust Protection Unit (TPU)429
- Dedicated Cryptographic DMA Engine (CDMA)430
  - Figure 23-1. Cryptographic Accelerator Block Diagram430
  - Fifos431
  - Figure 23-2. DMA Block Diagram431
  - Table 23-1. Cryptographic Accelerator DMA Sources431
  - Cache Security432
  - Direct FIFO Access432
- Block Cipher Accelerator432
  - Figure 23-3. Block Cipher Block Diagram433
  - Table 23-2. Symmetric Block Ciphers433
  - Cipher Key Storage and Initialization434
  - Operation435
- Hash Function Accelerator435
  - Last Message Block Padding436
  - Figure 23-4. Block Cipher Diagram436
  - Table 23-3. Hash Functions436
- CRC Engine (Galois Field Accelerator)437
- Hamming Code Accelerator437
- Figure 23-5. Hamming XOR Calculations438
- Modular Arithmetic Accelerator439
  - Operation440
  - MAA Memory440
  - Table 23-4. Cryptographic Memory Segments440
  - Table 23-5. MAA Memory Segments and Locations441
  - Table 23-6. MAA Memory Blinding Example (Memory Instance 0, MAWS > 1024)441
- True Random Number Generation442
- Registers442
  - Write Access443
  - Read Access443
  - Table 23-7. Cryptographic Registers, Offsets and Descriptions443
- Register Details444
- Table 23-8: Cryptographic Control Register444
- Table 23-9: Cipher Control Register446
- Table 23-10: Hash Control Register447
- Table 23-11: CRC Control Register448
- Table 23-12: Cryptographic DMA Source Register449
- Table 23-13: Cryptographic DMA Destination Register449
- Table 23-14: Cryptographic DMA Count Register449
- Table 23-15: MAA Control Register449
- Table 23-16: Cryptographic Data Input Register452
- Table 23-17: Cryptographic Data Output Register452
- Table 23-18: CRC Polynomial Register453
- Table 23-19: CRC Value Register453
- Table 23-20: CRC PRNG Register453
- Table 23-21: Hamming Error Correction Code Register453
- Table 23-22: Cipher Initial Vector Register [3:0]453
- Table 23-23: Cipher Key Register [7:0]454
- Table 23-24: HASH Message Digest Register [15:0]454
- Table 23-25: Hash Message Size Registers454
- Table 23-26: MAA Word Size Register455
- Table 23-27: TRNG Control Register (Base Address 0X400B_5000)456
- Table 23-28: TRNG Data Register (Base Address 0X400B_5000)456
24 Revision History457

Maxim Integrated MAX32665 - Figure 4-4: DEEPSLEEP Clock Control

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