MAX32665-MAX32668 User Guide
Maxim Integrated Page 295 of 457
Master Mode I
2
C Bus Transaction Active
The peripheral is operating in Master mode and a valid transaction beginning with a
START command is in progress on the I
2
C bus. This bit will read 1 until the master ends
the transaction with a STOP command. This bit will continue to read 1 while a slave
performs clock stretching.
0: Device not actively driving SCL clock cycles.
1: Device operating as master and actively driving SCL clock cycles.
TX FIFO Full
0: Not full
1: Full
TX FIFO Empty
0: Not empty
1: Empty
RX FIFO Full
0: Not full
1: Full
RX FIFO Empty
0: Not empty
1: Empty
Master or Slave Mode I
2
C Bus Transaction Active
The peripheral is operating in Master or Slave mode and a valid transaction beginning
with a START command is in progress on the I2C bus. This bit will read 1 until the
peripheral acting as a master or an external master ends the transaction with a STOP
command. This bit will continue to read 1 while a slave performs clock stretching.
0: I
2
C bus is idle.
1: I
2
C bus transaction in progress.
Table 13-8: I
2
C Interrupt Flag 0 Register
Slave Write Address Match Interrupt Flag
If set, the device has been accessed for a write (i.e. receive) transaction in slave
mode and the address received matches the device slave address.
0: No address match.
1: Address match.
Slave Read Address Match Interrupt Flag
If set, the device has been accessed for a read (i.e. transmit) transaction in slave
mode and the address received matches the device slave address.
0: No address match.
1: Address match.
TX FIFO Locked Interrupt Flag
If set, the TX FIFO is locked and writes to the TX FIFO are ignored. When set, the TX
FIFO is automatically flushed. Writes to the TX FIFO are ignored until this flag is
cleared. Write 1 to clear.
0: TX FIFO not locked.
1: TX FIFO is locked and all writes to the TX FIFO are ignored.
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