Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 447 of 457
Cipher Control Register
CIPHER_CTRL
[0x0004]
BITS
NAME
ACCESS
RESET
DESCRIPTION
10:8
mode
R/W
0
Mode Select
Operating mode of block cipher or memory operation.
0b000: ECB
0b001: CBC
0b010: CFB
0b011: OFB
0b100: CTR
Others: Reserved
7
-
RO
0
Reserved for Future Use
Do not modify this field from its default value.
6:4
cipher
R/W
0
Block Cipher Operation Select
Symmetric Block Cipher algorithm selection or memory operation.. Clear these bits
before starting any other operation of the cryptographic accelerator.
0b000: Disabled
0b001: AES-128
0b010: AES-192
0b011: AES-256
0b100: DES
0b101: TDEA
0b110: Reserved
0b111: Reserved
3:2
src
R/W
0
Source of Cipher Key
This indicates the source of the key data to be loaded into CIPHER_KEY_7:0 registers
when the CIPHER_CTRL.key bit is set. Each field setting loads 128 bits. The load cipher
key operation must be performed twice (once with 0b10 and again with 0b11) to load
a full 256-bit key.
0b00: CIPHER_KEY_7:0
0b01: CIPHER_KEY_7
0b10: AES_KEY2
0b11: AES_KEY3
1
key
R/W1O
0
Load Cipher Key Using CMDA
Setting this bit initiates loading of the CIPHER_KEY[7:0] registers with the contents
pointed to by CIPHER_CTRL.src. The bit must be cleared and the
CRYPTO_CTRL.dma_done bit after the DMA completes loading the key.
0: NOP
1: Initiate key loading from DMA
0
enc
R/W
0
Encryption Mode
Select encryption or decryption of block cipher data.
0: Encrypt
1: Decrypt
Table 23-10: Hash Control Register
Hash Control Register
HASH_CTRL
[0x08]
BITS
NAME
ACCESS
RESET
DESCRIPTION
31:6
-
RO
0
Reserved for Future Use
Do not modify this field from its default value.

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English