9.2 DMA Channel Operation (DMACH)
9.2.1 DMA Channel Arbitration and DMA Bursts
DMAC contains an internal arbiter that allows enabled channels to access the AHB and move data. Once a channel is
programmed and enabled, it generates a request to the arbiter immediately (for memory-to-memory DMA) or whenever its
associated peripheral requests DMA (for memory-to-peripheral or peripheral-to-memory DMA).
Granting is done based on priority—a higher priority request is always granted. Within a given priority level, requests are
granted on a round-robin basis. The DMACHn_CFG.priority field determines the DMA channel priority.
When a channel’s request is granted, it runs a DMA transfer. The arbiter grants requests to a single channel at a time. Once
the DMA transfer completes, the channel relinquishes its grant.
A DMA channel is enabled using the DMACHn_CFG.chen bit.
When disabling a channel, poll the DMACHn_ST.ch_st bit to determine if the channel is truly disabled. In general,
DMACHn_ST.ch_st follows the setting of the DMACHn_CFG.chen bit. However, the DMACHn_ST.ch_st bit is automatically
cleared under the following conditions:
• Bus error (cleared immediately)
• CTZ when the DMACHn_CFG.rlden = 0 (cleared at the end of the AHB R/W burst)
• DMACHn_CFG.chen bit transitions to 0 (cleared at the end of the AHB R/W burst)
Whenever DMACHn_ST.ch_st transitions from 1 to 0, the corresponding DMACHn_CFG.chen bit is also cleared. If an active
channel is disabled during an AHB read/write burst, the current burst will continual until completed.
Only an error condition can interrupt an ongoing data transfer.
To Next Page
Loading...
Need help?
General