MAX32665-MAX32668 User Guide
Maxim Integrated Page 222 of 457
9. Standard DMA (DMAC)
The Standard Direct Memory Access controller (DMAC) is a hardware feature that provides the ability to perform high-
speed, block memory transfers of data independent of an Arm core. All DMAC transactions consist of burst read from the
source into the internal DMA FIFO followed by an burst write from the internal DMA FIFO to the destination.
DMA transfers are one of three types:
• From a receive FIFO to a memory address
• To a transmit FIFO from a memory address, or
• From a source memory address to a destination memory address.
The DMAC supports multiple channels. Each channel provides the following features:
• Full 32-bit source and destination addresses with 24-bit (16 Mbytes) address increment capability
• Ability to chain DMA buffers when a count-to-zero (CTZ) condition occurs
• Up to 16 Mbytes for each DMA transfer
• 8 x 32 byte transmit and receive FIFO
• Programmable channel timeout period
• Programmable burst size
• Programmable priority
• Interrupt upon CTZ
• Abort on error
9.1 Instances
There are two instances of the DMAC, generically referred to as DMACm. Each instance provides 8 channels, generically
referred to as DMACHn. Each instance of the DMAC has a set of interrupt registers common to all its channels, and a set of
registers unique to each channel instance.
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