EasyManua.ls Logo

Maxim Integrated MAX32665 - Table 2-3: MAX32665-MAX32668 AHB Slaves; Table 2-4. MAX32665-MAX32668 AHB Master;Slave Interconnect Matrix

Maxim Integrated MAX32665
457 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
MAX32665-MAX32668 User Guide
Maxim Integrated Page 27 of 457
AHB
Master
Bit Position in SLAVEAPB Register
Bit Position in
SLAVEAHB Register
Write
Read
Write
Read
SYS0
access[3]
access[7]
access[6]
SYS1
access[4]
access[9]
access[8]
SDMAD
access[6]
access[11]
access[10]
SDMAI
access[7]
access[13]
access[12]
CRYPTO
access[8]
access[15]
access[14]
SDIO
access[9]
access[17]
access[16]
Table 2-3 lists the AHB slaves addressable by AHB bus masters. Each AHB slave has a dedicated RPU access control register
similar to the APB RPU access control registers, but each AHB slave has two control bits.
Table 2-3: MAX32665MAX32668 AHB Slaves
AHB Slave
Address
Description
USBHS
USB FIFO
USB Endpoint Data
SDIO/SDHC Target
SDIO/SDHC Target Memory
SDIO/SDHC Target Memory
SPIM
SPI FIFO Memory
SPI Bus Master FIFO
QSPI/SPI
QSPI FIFO
QSPI Data Buffer
SYS_RAM (MI0)
Configurable by Arm MPU
System RAM, Memory Instance 0
SYS_RAM (MI1)
Configurable by Arm MPU
System RAM, Memory Instance 1
SYS_RAM (MI2)
Configurable by Arm MPU
System RAM, Memory Instance 2
SYS_RAM (MI3)
Configurable by Arm MPU
System RAM, Memory Instance 3
SYS_RAM (MI4)
Configurable by Arm MPU
System RAM, Memory Instance 4
SYS_RAM (MI5)
Configurable by Arm MPU
System RAM, Memory Instance 5
SYS_RAM (MI6)
Configurable by Arm MPU
System RAM, Memory Instance 6
The AHB bus prohibits some AHB master and slave interactions as shown in Table 2-4. The AHB slave ignores the state of
prohibited combinations.
Table 2-4. MAX32665MAX32668 AHB Master/Slave Interconnect Matrix
AHB Slave
AHB Master
DMAC0
DMAC1
USB
SYS0
SYS1
SDMAD
SDMAI
CRYPTO
SDIO/SDHC
MASTER
SYS_RAM (MI0)
Y
Y
Y
Y
Y
Y
Y
Y
Y
SYS_RAM (MI1)
Y
Y
Y
Y
Y
Y
Y
Y
Y
SYS_RAM (MI2)
Y
Y
Y
Y
Y
Y
Y
Y
Y
SYS_RAM (MI3)
Y
Y
Y
Y
Y
Y
Y
Y
Y
SYS_RAM (MI4)
Y
Y
Y
Y
Y
Y
Y
Y
Y
SYS_RAM (MI5)
Y
Y
Y
Y
Y
Y
Y
Y
Y
SYS_RAM (MI6)
Y
Y
Y
Y
Y
Y
Y
Y
Y

Table of Contents