MAX32665-MAX32668 User Guide
Maxim Integrated Page 173 of 457
SPIXR Master Baud Rate Generator Register
SCK Low Clock Cycles Control
Setting this field to 0 disables the low duty cycle control for SCK.
Setting this field to any non-zero value sets the high cycle time to:
Note: If SPIXR_BRG_CTRL.scale = 0, SPIXR_BRG_CTRL.hi = 0, and
SPIXR_BRG_CTRL.lo = 0, character sizes of 2 and 10 bits are not supported.
Table 8-31. SPIXR DMA Control Register
SPIXR DMA Control Register
RX DMA Enable
Enable or disable the RX DMA.
0: RX DMA is disabled. Any pending DMA requests are cleared
1: RX DMA is enabled
Reserved for Future Use
Do not modify this field.
Number of Bytes in the RX FIFO
Reading this field returns the number of bytes currently in the RX FIFO
Clear the RX FIFO
Set this field to clear the RX FIFO and all related RX FIFO flags in the
SPIXR_INT_FL register. When cleared, the SPIXR_INT_FL.rx_fifo_empty flag is set
by hardware.
1: Clear the RX FIFO and any pending RX FIFO flags in SPIXR_INT_FL. This
should be done when the RX FIFO is inactive.
Note: Writing 0 has no effect.
RX FIFO Enabled
Set this field to 1 to enable the RX FIFO.
0: RX FIFO disabled
1: RX FIFO enabled
Reserved for Future Use
Do not modify this field.
RX FIFO Threshold Level
When the RX FIFO has more than this field, a DMA request is triggered, and the
SPIXR_INT_FL.rx_level interrupt flag is set. Valid values are 0x00 to 0x1E.
0x1F is not a valid value.
TX DMA Enable
0: TX DMA is disabled. Any pending DMA requests are cleared.
1: TX DMA is enabled
Reserved for Future Use
Do not modify this field.
Number of Bytes in the TX FIFO
Read returns the number of bytes currently in the TX FIFO