Maxim Integrated MAX32665 - Table 14-17: Qspin Wakeup Enable Registers; Table 14-18: Qspin Slave Select Timing Registers

MAX32665-MAX32668 User Guide
Maxim Integrated Page 323 of 457
Table 14-17: QSPIn Wakeup Enable Registers
QSPIn Wakeup Enable Register
QSPIn_WAKE_EN
[0x002C]
Bits
Name
Access
Reset
Description
31:4
-
R/W
0
Reserved for Future Use
Do not modify this field.
3
rx_full
R/W
0
Wake on RX FIFO Full Enable
0: Wake event is disabled
1: Wake event is enabled.
2
rx_thresh
R/W
0
Wake on RX FIFO Threshold Level Crossed Enable
0: Wake event is disabled
1: Wake event is enabled.
1
tx_empty
R/W
0
Wake on TX FIFO Empty Enable
0: Wake event is disabled
1: Wake event is enabled.
0
tx_thresh
R/W
0
Wake on TX FIFO Threshold Level Crossed Enable
0: Wake event is disabled
1: Wake event is enabled.
Table 14-18: QSPIn Slave Select Timing Registers
QSPIn Status Register
QSPIn_STAT
[0x0030]
Bits
Name
Access
Reset
Description
31:1
-
R/W
0
Reserved for Future Use
Do not modify this field.
0
busy
R
0
SPI Active Status
0: QSPIn is not active. In master mode the busy flag is cleared when the last
character is sent. In slave mode the busy field is cleared when the configured
slave select input is deasserted.
1: QSPIn is active. In master mode the busy flag is set when a transaction starts. In
slave mode the busy flag is set when a configured slave select input is asserted.