Maxim Integrated MAX32665 - Table 8-66: SDHC Host Control 1 Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 196 of 457
Present State Register
SDHC_PRESENT
[0x0024]
Bits
Name
Access
Reset
Description
1
dat
RO
0
Command Inhibit (DAT)
This bit is set if DAT Line Active or the Read Transfer Active bits are set. A SDHC_IRQ
interrupt is generated, if enabled, when this bit transitions from a 1 to a 0 with the
SDHC_INT_STAT.trans_comp flag set. The card driver can save registers in the range
of 0x000 to 0x00D for a suspend transaction after the SDHC_INT_STAT.trans_comp
interrupt event.
1: Command that uses DAT line cannot be issued.
0: Command that uses DAT line can be issued.
0
cmd_comp
RO
0
Command Inhibit (CMD)
If this bit reads 0, the CMD line is not in use. This bit is set to 1 by the SDHC
immediately after the SDHC_CMD register is written, and the bit is cleared to 0 when
the Command Response is received. Auto CMD12 and Auto CMD23 consist of two
responses, and this bit is not cleared until the read/write portion of the sequence is
complete.
1: Command cannot be issued.
0: Can issue command using only CMD line.
Table 8-66: SDHC Host Control 1 Register
Host Control 1 Register
SDHC_HOST_CN_1
[0x0028]
Bits
Name
Access
Reset
Description
7
card_detect_signal
R/W
0
Card Detect Signal Selection
1: The Card Detect Test Level is selected (for test purposes)
0: SDHC_CDN is used for card detection (normal operation)
Note: Disable the Card Detect Interrupt when changing this bit.
6
card_detect_test
R/W
-
Card Detect Test Level
This bit is enabled when the Card Detect Signal Selection, SDHC_HOST_CN_1.
card_detect_signal, field is set to 1.
1: Card Inserted
0: No card inserted
5
ext_data_transfer_width
R/W
0
Extended Data Transfer Width
Extended data transfer width is not supported on the MAX32665—MAX32668.
Always reads 0.
0: Bus width is selected by SHDC_HOST_CN_1.data_transfer_width field
4:3
dma_select
R/W
0
DMA Select
Sets the DMA mode.
0b00: SDMA mode
0b01: Reserved
0b10: 32-bit address ADMA2 mode
0b11: Reserved
2
hs_en
R/W
0
High Speed Enable
1: High-speed mode
0: Normal-speed mode
1
data_transfer_width
R/W
0
Data Transfer Width
Sets the data transfer width of the SDHC.
1: 4-bit mode
0: 1-bit mode