Maxim Integrated MAX32665 - Table 4-35: Buck Cycle Count Alert VREGO_D Register; Table 4-36: Buck Regulator Output Ready Register; Table 4-37: Zero Cross Calibration VREGO_A Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 77 of 457
Table 4-35: Buck Cycle Count Alert VREGO_D Register
Buck Cycle Count Alert VREGO_D
BUCK_ALERT_THR_D
[0x003C]
Bits
Field
Access
Reset
Description
31:8
-
RO
-
Reserved
Do not modify this field.
7:0
buckthrd
R/W
0
Reserved
Reserved. Do not modify this field.
Table 4-36: Buck Regulator Output Ready Register
Buck Regulator Output Ready
BUCK_OUT_READY
[0x0040]
Bits
Field
Access
Reset
Description
31:4
-
RO
-
Reserved
Do not modify this field.
3
buckoutrdya
RO
0
VREGO_A Output Ready
When VREGO_A.vseta changes, this bit will be set when the output voltage has
reached its regulated value. It will not be cleared if the output voltage drops
below its set value.
0: Not ready
1: Ready
2
buckoutrdyb
RO
0
VREGO_B Output Ready
When VREGO_B.vsetb changes, this bit will be set when the output voltage has
reached its regulated value. It will not be cleared if the output voltage drops
below its set value.
0: Not ready
1: Ready
1
buckoutrdyc
RO
0
VREGO_C Output Ready
When VREGO_C.vsetc changes, this bit will be set when the output voltage has
reached its regulated value. It will not be cleared if the output voltage drops
below its set value.
0: Not ready
1: Ready
0
buckoutrdyd
RO
0
VREGO_D Output Ready
When VREGO_D.vsetd changes, this bit will be set when the output voltage has
reached its regulated value. It will not be cleared if the output voltage drops
below its set value.
0: Not ready
1: Ready
Table 4-37: Zero Cross Calibration VREGO_A Register
Zero Cross Calibration VREGO_A
ZERO_CROSS_CAL_A
[0x0044]
Bits
Field
Access
Reset
Description
31:5
-
RO
-
Reserved
Do not modify this field.
4:0
zxcala
RO
0
Reserved
Reserved. Do not modify this field.