MAX32665-MAX32668 User Guide
Maxim Integrated Page 231 of 457
The start of the timeout period is controlled by DMACHn_CFG.reqwait:
• If DMACHn_CFG.reqwait = 0, the timer begins counting immediately after DMACHn_CFG.to_sel is configured to a
value other than 0x0.
• If DMACHn_CFG.reqwait = 1, the timer begins counting when the first DMA request is received from the
peripheral.
The timer is reset whenever:
• The DMA request line programmed for the channel is activated.
• The channel is disabled for any reason (DMACHn_ST.ch_st = 0).
If the timeout timer period expires, hardware will set DMACHn_ST.to_st = 1 to indicate a channel timeout event has
occurred. A channel timeout will not disable the DMA channel.
9.8 Memory-to-Memory DMA
Memory-to-memory transfers are processed as if the request is always active. This means that the DMA channel generates
an almost constant request for the bus until its transfer is complete. For this reason, assign a lower priority to channels
executing memory-to-memory transfers to prevent starvation of other DMA channels.
9.9 DMAC Registers
See Table 3-1: APB Peripheral Base Address Map for this peripheral/module's base address. If multiple instances are
provided, each will have a unique base address. Unless specified otherwise, all fields are reset on a system reset, soft reset,
POR, and the peripheral-specific reset, if applicable.
Table 9-6: DMAC Register Summary
DMACn Channel Interrupt Enable
Each bit in this field enables the corresponding channel interrupt m in DMACn_INT.
Register bits associated with unimplemented channels should not be changed from
their default reset value.
0: Disabled.
1: Enabled.
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