MAX32665-MAX32668 User Guide
Maxim Integrated Page 40 of 457
3.3.3 External Memory Cache Controller (EMCC)
The SPIXR RAM interface is supported by a dedicated 16,384 Byte 2-way set-associative Least Recently Used (LRU) write-
through cache. This cache is managed through the EMCC interface.
3.3.4 Information Block Flash Memory
The information block is a separate flash instance of 16KB. It is used to store trim settings (option configuration and analog
trim) as well as other nonvolatile device-specific information intended for use by firmware.
3.3.5 System SRAM
The system SRAM is 560KB in size and can be used for general purpose data storage, the Arm system stack, USB data
transfers (endpoints), SD Host Controller (SDHC) interface, TPU and code execution if desired.
3.3.6 AES Key and Working Space Memory
The AES key memory and working space for AES operations (including input and output parameters) are in a dedicated
register file memory tied to the AES engine block. This AES memory is mapped into AHB space for rapid firmware access.
3.3.7 MAA Key and Working Space Memory
The MAA contains a dedicated memory for key storage, input and output parameters for operations, and working space. It
is mapped into the AHB memory space for ease of loading and unloading.
3.3.8 TPU Memory
The MAX32665—MAX32668 contains a specialized 128-bit memory that is designed to preserve critical data (such as a 128-
bit AES key) even when the device is in the lowest power-saving state. As long as the RTC power supply is still available, the
contents of this memory will be retained, even if the AES block and the main SRAM are shut down completely.
The Secure Key Storage Area consists of four V
RTC
supply backed 32-bit registers: TPU_TSR_SKS0, TPU_TSR_SKS1,
TPU_TSR_SKS2, and TPU_TSR_SKS3.
3.4 AHB Interfaces
This section details memory accessibility on the AHB and the organization of AHB master and slave instances.
3.4.1 Core AHB Interfaces
3.4.1.1 I-Code
This AHB master is used by the Arm core for instruction fetching from memory instances located in code space from byte
addresses 0x0000 0000 to 0x1FFF FFFF. This bus master is used to fetch instructions from the internal flash memory and the
external SPIF flash memory (if SPIXF is enabled). Instructions fetched by this bus master are returned by the instruction
cache, which in turn triggers a cache line fill cycle to fetch instructions from the internal flash memory or the external SPIXF
flash memory when a cache miss occurs.
3.4.1.2 D-Code
This AHB master is used by the Arm core for data fetches from memory instances located in code space from byte
addresses 0x0000 0000 to 0x1FFF FFFF. This bus master has access to the internal flash memory, the external SPIXF flash
memory (if SPIXF is enabled), and the information block.
3.4.1.3 System
This AHB master is used by the Arm core for all instruction fetches and data read and write operations involving the SRAM
data cache. The APB mapped peripherals (through the AHB-to-APB bridge) and AHB mapped peripheral and memory areas
are also accessed using this bus master.
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