MAX32665-MAX32668 User Guide
Maxim Integrated Page 272 of 457
13. I
2
C Master/Slave Serial Communications Peripheral (I2C)
The I2C peripherals can be configured as either an I
2
C master or I
2
C slave at standard data rates. For simplicity, I2Cn is used
throughout this section to refer to any of the I2C peripherals.
The MAX32665—MAX32668 has the ability to access the I2Cn peripherals via two different busses (clock sources). Bus 0 is
the traditional I
2
C implementation where the peripheral timing is based on the synchronous APB clock (f
SYS_CLOCK
divided by
2). Obviously, as the system clock is changed, the timing for the I2Cn peripherals change as well. Managing the timing for
I
2
C can become complex if the system clock is ever changed, especially real-time, for example when trying to maximize
battery life. Bus 1, on the other hand, provides access to the I2Cn peripherals via an asynchronous APB bus running at a
fixed frequency, 7.3728MHz, and simplifies the management of the I2Cn peripherals being that their timing is not
dependent on a clock which may change real-time.
The user selects the desired bus by using either the I2Cn registers designated BUS 0 or designated BUS 1. The registers for
each of the bus instances are identical except for the base address. Likewise, the registers for each of the I2Cn peripherals
are identical except for the base addresses. The base addresses are illustrated in Figure 12-1: UART Frame Diagram.
For detailed information on I
2
C bus operation, refer to Maxim Application Note 4024 “SPI/I²C Bus Lines Control Multiple
Peripherals” https://www.maximintegrated.com/en/app-notes/index.mvp/id/4024
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