Maxim Integrated MAX32665 - CRC Engine (Galois Field Accelerator); Hamming Code Accelerator

MAX32665-MAX32668 User Guide
Maxim Integrated Page 437 of 457
For SHA-1 and SHA-256, a single bit equal to 1 is appended to the end of the message. The message is then padded using
software with zeros until 64 bits remain in the last 512-bit block. If less than 64 bits remain, then zeros are appended to the
message until 64 bits remain in the next 512-bit block. The HASH_CTRL.last field is set along with HASH_MSG_SZ_[1:0].
Hardware appends values in these registers to the last 64 bits of the final message block.
For SHA-384 and SHA-512, a single bit equal to 1 is appended to the end of the message. The message is then padded with
zeros until 128 bits remain in the last 1024-bit block. If less than 128 bits remain, then zeros are appended to the message
until 128 bits remain in the next 1024-bit block. The HASH_CTRL.last is set along with HASH MSG_SZ_0.
The automatic padding feature is used in terms of message bytes, not bits. Therefore, the HASH MSG_SZ_0 are expressed in
bytes. In addition, the feature automatically generates an additional padding-only block if the last block of message data
cannot accommodate the 64- or 128-bit padding block.
As an exception, attempting to hash a 0 message-size block must include a dummy write to the HASH message digest
register.
Hash operations using the CMDA set CRYPTO_CTRL.hsh_done=1 and CRYPTO_CTRL.dma_done = 1, and
CRYPTO_CTRL.done=1 when complete.
23.4 CRC Engine (Galois Field Accelerator)
Registers pertaining to CRC functionality are included in the TPU register space, but are covered in a separate chapter. See
the CRC chapter for information about using the CRC.
23.5 Hamming Code Accelerator
The Hamming code accelerator calculates an Error Correction Code (ECC) on a block of data. Hamming codes are capable of
correcting single-bit errors. You can include an extra parity bit to detect two-bit errors. This is commonly referred to as
Signal Error Correction, Double Error Detection (SEC-DED). Three errors masquerade as a correctable, single-bit error.
Multi-level Cell (MLC) Flash memories require Error Correction Codes that can correct multiple-bit errors since a corrupt cell
can have multiple bit errors.
The hardware can calculate ECCs for a block of data up to 216 bits in length (8kB), but software implementations can
extend this to any length. Because the Hamming code can only correct a single-bit error, increasing the block size increases
the likelihood of multiple errors that are uncorrectable. The Hamming code generator in the cryptographic accelerator
generates even parity on even halves of bit groups.
If you want the parity of the odd halves of the bit groups, XOR the parity of the even halves with the parity of the entire
array. If the parity of the entire array is odd, the parity of the odd halves is the inverse of the parity of the even halves. If the
parity of the entire array is even, the parity of the odd halves is identical to the parity of the even halves.