MAX32665-MAX32668 User Guide
Maxim Integrated Page 66 of 457
Cache Release Number
Returns the release number for this Cache instance.
Table 4-10: SFCC Memory Size Register
Addressable Memory Size
Indicates the size of addressable memory by this cache controller instance in
128KB units.
Cache Size
Returns the size of the cache RAM memory in 1KB units.
16: 16KB Cache RAM
Table 4-11: SFCC Cache Control Register
Reserved
Do not modify this field.
Ready
This field is cleared by hardware anytime the cache as a whole is invalidated
(including a Power On Reset event). Hardware automatically sets this field to 1
when the invalidate operation is complete and the cache is ready.
0: Cache Invalidate in process.
1: Cache is ready.
Note: While this field reads 0, the cache is bypassed and reads come directly from
the line fill buffer.
Reserved
Do not modify this field.
Enable
Set this field to 1 to enable the cache. Setting this field to 0 automatically
invalidates the cache contents. When this cache is disabled, reads are handled by
the line fill buffer.
0: Disable cache
1: Enable cache
Table 4-12: SFCC Invalidate Register
Invalidate
Any write to this register of any value invalidates the cache.
4.7 External RAM SPIXR Cache Controller (SRCC)
See Section 8.4 SPIXR Cache Controller (SRCC) for detailed usage information for the SRCC and the SRCC register interface.
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