MAX32665-MAX32668 User Guide
Maxim Integrated Page 78 of 457
Table 4-38: Zero Cross Calibration VREGO_B Register
Zero Cross Calibration VREGO_B
Reserved
Do not modify this field.
Reserved
Reserved. Do not modify this field.
Table 4-39: Zero Cross Calibration VREGO_C Register
Zero Cross Calibration VREGO_C
Reserved
Do not modify this field.
Reserved
Reserved. Do not modify this field.
Table 4-40: Zero Cross Calibration VREGO_D Register
Zero Cross Calibration VREGO_D
Reserved
Do not modify this field.
Reserved
Reserved. Do not modify this field.
4.14 Power Sequencer and Always-On Domain Registers
See Table 3-1: APB Peripheral Base Address Map for the Power Sequencer Peripheral Base Address.
Table 4-41: Power Sequencer and Always-On Domain Register Summary
Low Power Control Register
GPIO0 Low Power Wakeup Status Flags
GPIO0 Low Power Wakeup Enable Register
GPIO1 Low Power Wakeup Status Flags
GPIO1 Low Power Wakeup Enable Register
Peripheral Low Power Wakeup Status Flags
Peripheral Low Power Wakeup Enable Register
RAM Shutdown Control Register
VDD Low Power Domain Control Register
BACKUP Return Vector Register
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