Maxim Integrated MAX32665 - Power Sequencer and Always-On Domain Registers; Table 4-38: Zero Cross Calibration VREGO_B Register; Table 4-39: Zero Cross Calibration VREGO_C Register; Table 4-40: Zero Cross Calibration VREGO_D Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 78 of 457
Table 4-38: Zero Cross Calibration VREGO_B Register
Zero Cross Calibration VREGO_B
ZERO_CROSS_CAL_B
[0x0048]
Bits
Field
Access
Reset
Description
31:5
-
RO
-
Reserved
Do not modify this field.
4:0
zxcalb
RO
0
Reserved
Reserved. Do not modify this field.
Table 4-39: Zero Cross Calibration VREGO_C Register
Zero Cross Calibration VREGO_C
ZERO_CROSS_CAL_C
[0x004C]
Bits
Field
Access
Reset
Description
31:5
-
RO
-
Reserved
Do not modify this field.
4:0
zxcalc
RO
0
Reserved
Reserved. Do not modify this field.
Table 4-40: Zero Cross Calibration VREGO_D Register
Zero Cross Calibration VREGO_D
ZERO_CROSS_CAL_D
[0x0050]
Bits
Field
Access
Reset
Description
31:5
-
RO
-
Reserved
Do not modify this field.
4:0
zxcald
RO
0
Reserved
Reserved. Do not modify this field.
4.14 Power Sequencer and Always-On Domain Registers
See Table 3-1: APB Peripheral Base Address Map for the Power Sequencer Peripheral Base Address.
Table 4-41: Power Sequencer and Always-On Domain Register Summary
Offset
Register
Name
[0x0000]
PWRSEQ_LPCN
Low Power Control Register
[0x0004]
PWRSEQ_LPWKST0
GPIO0 Low Power Wakeup Status Flags
[0x0008]
PWRSEQ_LPWKEN0
GPIO0 Low Power Wakeup Enable Register
[0x000C]
PWRSEQ_LPWKST1
GPIO1 Low Power Wakeup Status Flags
[0x0010]
PWRSEQ_LPWKEN1
GPIO1 Low Power Wakeup Enable Register
[0x0030]
PWRSEQ_LPPWST
Peripheral Low Power Wakeup Status Flags
[0x0034]
PWRSEQ_LPPWEN
Peripheral Low Power Wakeup Enable Register
[0x0040]
PWRSEQ_LPMEMSD
RAM Shutdown Control Register
[0x0044]
PWRSEQ_LPVDDPD
VDD Low Power Domain Control Register
[0x0048]
PWRSEQ_BURET
BACKUP Return Vector Register
[0x004C]
PWRSEQ_BUAOD
BACKUP AoD Register