MAX32665-MAX32668 User Guide
Maxim Integrated Page 277 of 457
13.4 I
2
C Configuration and Usage
13.4.1 SCL and SDA Bus Drivers
SCL and SDA are open-drain signals. In this device, once the I
2
C peripheral is enabled and the proper GPIO alternate
function is selected, the corresponding pad circuits are automatically configured as open-drain outputs. However, SCL can
also be optionally configured as a push-pull driver to conserve power and avoid the need for any pullup resistor. This should
only be used in systems where no I
2
C slave device can hold SCL low, such as for clock stretching. Push-pull operation is
enabled by setting I2Cn_CTRL0.sclppm to 1. SDA, on the other hand, always operates in open-drain mode.
13.4.2 SCL Clock Configurations
The SCL frequency is dependent upon the values of I
2
C peripheral clock and the values of the external pullup resistor and
trace capacitance on the SCL clock line.
Note: An external RC load on the SCL line will affect the target SCL frequency calculation.
13.4.3 SCL Clock Generation for Standard, Fast and Fast-Plus Modes
The master generates the I
2
C clock on the SCL line. When operating as a master, application code must configure the
I2Cn_CLK_HI and I2Cn_CLK_LO registers for the desired I
2
C operating frequency.
The MAX32665—MAX32668 has the ability to select the source for the I
2
C peripheral clock. Application code can select
between the system peripheral clock,
(accessed via I2Cn Bus 0 registers), or the 7.3728MHz oscillator (accessed via
I2Cn Bus 1 registers). The frequency
is
divided by 2. All three I2Cn peripherals default to Bus 0. Switching one
or more of the peripherals to Bus 1 consists of first selecting the 7.3728MHz bus (GCR_APB_ASYNC.apbasyncI2Cn), followed
by accessing it via the corresponding I2Cn Bus 1 registers. The base address are shown in the block diagram shown in Figure
12-1: UART Frame Diagram.
The SCL high time is configured in the I
2
C Clock High Time register field I2Cn_CLK_HI.scl_hi using Equation 13-1. The SCL low
time is configured in the I
2
C Clock Low Time register field I2Cn_CLK_LO.scl_lo using Equation 13-2. Each of these fields is 8-
bits. The value
is either
or 7.3728MHz.
Equation 13-1: I
2
C Clock High Time Calculation
t
SCLHI
t
I2CCLK
sclhi 1
Equation 13-2: I
2
C Clock Low Time Calculation
t
SCLLO
t
I2CCLK
scllo 1
Figure 13-3 shows the association between the SCL clock low and high times for Standard, Fast and Fast Plus I
2
C
frequencies.
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