MAX32665-MAX32668 User Guide
Maxim Integrated Page 129 of 457
Table 6-22: GPIO Port n Interrupt Enable Register
GPIO Port n Interrupt Enable
GPIO Interrupt Enable
Enable or disable the interrupt for the corresponding GPIO pin.
0: GPIO interrupt disabled.
1: GPIO interrupt enabled.
Note: Disabling a GPIO interrupt does not clear pending interrupts for the associated
pin. Use the GPIOn_INT_CLR register to clear pending interrupts.
Table 6-23: GPIO Port n Interrupt Enable Atomic Set Register
GPIO Port Interrupt Enable Atomic Set
GPIO Interrupt Enable Atomic Set
Writing 1 to one or more bits sets the corresponding bits in the
GPIOn_INT_EN register.
0: No effect.
1: Corresponding bits in GPIOn_INT_EN register set to 1.
Table 6-24: GPIO Port n Interrupt Enable Atomic Clear Register
GPIO Port Interrupt Enable Atomic Clear
GPIO Interrupt Enable Atomic Clear
Writing 1 to one or more bits clears the corresponding bits in the
GPIOn_INT_EN register.
0: No effect.
1: Corresponding bits in GPIOn_INT_EN register cleared to 0.
Table 6-25: GPIO Port n Interrupt Status Register
GPIO Port Interrupt Status
GPIO Interrupt Status
An interrupt is pending for the associated GPIO pin when this bit reads 1.
0: No interrupt pending for associated GPIO pin.
1: GPIO interrupt pending for associated GPIO pin.
Note: Write a 1 to the corresponding bit in the GPIOn_INT_CLR register to clear the
interrupt pending status flag.
Table 6-26: GPIO Port n Interrupt Clear Register
GPIO Port Interrupt Clear
GPIO Interrupt Clear
Write 1 to clear the associated interrupt status (GPIOn_INT_STAT).
0: No effect on the associated GPIOn_INT_STAT flag.
1: Clear the associated interrupt pending flag in the GPIOn_INT_STAT register.
To Next Page
Loading...