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Maxim Integrated MAX32665 User Manual

Maxim Integrated MAX32665
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MAX32665-MAX32668 User Guide
Maxim Integrated Page 157 of 457
SPIXF Controller Interrupt Status Register
SPIXFC_INT_FL
[0x0014]
Bits
Name
Access
Reset
Description
0
tstall
R/W1C
0
Transmit Stalled Interrupt Flag.
This flag is set by hardware when the Transmit FIFO is empty, and the selected
slave select is asserted.
0: Normal FIFO.
1: Stalled FIFO.
Table 8-11. SPIXF Controller Interrupt Enable Register
SPIXF Controller Interrupt Enable Register
SPIXFC_INT_EN
[0x0018]
Bits
Name
Access
Reset
Description
31:6
-
R/W
0
Reserved for Future Use
Do not modify this field.
5
rfifoafie
R/W
0
Receive FIFO Almost Full Interrupt Enable.
Setting this bit enables interrupt generation when the SPIXFC_INT_FL.rfifoaf flag
is set. Clearing this bit means that no interrupt is generated.
0: Disable Receive FIFO Almost Full Interrupt
1: Enable Receive FIFO Almost Full Interrupt.
4
tfifoaeie
R/W
1
Transmit FIFO Almost Empty Interrupt Enable.
Setting this bit enables interrupt generation when the SPIXFC_INT_FL.tfifoae flag
is set. Clearing this bit means that no interrupt is generated.
0: Disable Transmit FIFO Almost Empty Interrupt.
1: Enable Transmit FIFO Almost Empty Interrupt.
3
rdoneie
R/W
0
Receive Done Interrupt Enable.
Setting this bit enables interrupt generation when the SPIXFC_INT_FL.rdone flag
is set. Clearing this bit means that no interrupt is generated.
0: Disable Receive Done Interrupt.
1: Enable Receive Done Interrupt.
2
trdyie
R/W
0
Transmit Ready Interrupt Enable.
Setting this bit enables interrupt generation when the SPIXFC_INT_FL.trdy flag is
set. Clearing this bit means that no interrupt is generated.
0: Disable Transmit Ready Interrupt.
1: Enable Transmit Ready Interrupt.
1
rstallie
R/W
0
Receive Stalled Interrupt Enable.
Setting this bit enables the Receive Stalled Interrupt. Clearing this bit means that
no interrupt is generated.
0: Disable Receive Stalled Interrupt.
1: Enable Receive Stalled Interrupt.
0
tstallie
R/W
0
Transmit Stalled Interrupt Enable.
Setting this bit enables interrupt generation when the SPIXFC_INT_FL.tstall flag
is set. Clearing this bit means that no interrupt is generated.
0: Disable Transmit Stalled Interrupt.
1: Enable Transmit Stalled Interrupt.

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Maxim Integrated MAX32665 Specifications

General IconGeneral
BrandMaxim Integrated
ModelMAX32665
CategoryMotherboard
LanguageEnglish