MAX32665-MAX32668 User Guide
Maxim Integrated Page 157 of 457
SPIXF Controller Interrupt Status Register
Transmit Stalled Interrupt Flag.
This flag is set by hardware when the Transmit FIFO is empty, and the selected
slave select is asserted.
0: Normal FIFO.
1: Stalled FIFO.
Table 8-11. SPIXF Controller Interrupt Enable Register
SPIXF Controller Interrupt Enable Register
Reserved for Future Use
Do not modify this field.
Receive FIFO Almost Full Interrupt Enable.
Setting this bit enables interrupt generation when the SPIXFC_INT_FL.rfifoaf flag
is set. Clearing this bit means that no interrupt is generated.
0: Disable Receive FIFO Almost Full Interrupt
1: Enable Receive FIFO Almost Full Interrupt.
Transmit FIFO Almost Empty Interrupt Enable.
Setting this bit enables interrupt generation when the SPIXFC_INT_FL.tfifoae flag
is set. Clearing this bit means that no interrupt is generated.
0: Disable Transmit FIFO Almost Empty Interrupt.
1: Enable Transmit FIFO Almost Empty Interrupt.
Receive Done Interrupt Enable.
Setting this bit enables interrupt generation when the SPIXFC_INT_FL.rdone flag
is set. Clearing this bit means that no interrupt is generated.
0: Disable Receive Done Interrupt.
1: Enable Receive Done Interrupt.
Transmit Ready Interrupt Enable.
Setting this bit enables interrupt generation when the SPIXFC_INT_FL.trdy flag is
set. Clearing this bit means that no interrupt is generated.
0: Disable Transmit Ready Interrupt.
1: Enable Transmit Ready Interrupt.
Receive Stalled Interrupt Enable.
Setting this bit enables the Receive Stalled Interrupt. Clearing this bit means that
no interrupt is generated.
0: Disable Receive Stalled Interrupt.
1: Enable Receive Stalled Interrupt.
Transmit Stalled Interrupt Enable.
Setting this bit enables interrupt generation when the SPIXFC_INT_FL.tstall flag
is set. Clearing this bit means that no interrupt is generated.
0: Disable Transmit Stalled Interrupt.
1: Enable Transmit Stalled Interrupt.