MAX32665-MAX32668 User Guide
Maxim Integrated Page 124 of 457
Each GPIO pin has a dedicated status bit in its corresponding GPIOn_INT_STAT register. A GPIO interrupt will occur when
the a status bit transitions from 0 to 1 if the corresponding bit is set in the corresponding GPIOn_INT_EN register. Note that
the interrupt status bit will always be set when the current interrupt configuration event occurs, but an interrupt will only
be generated if explicitly enabled.
The following procedure details the steps for enabling ACTIVE mode interrupt events for a GPIO pin:
1. Disable interrupts by setting the GPIOn_INT_EN[pin] field to 0. This will prevent any new interrupts on the pin from
triggering but will not clear previously triggered (pending) interrupts. The application can disable all interrupts for
a GPIO port by writing 0 to the GPIOn_IN_EN register. To maintain previously enabled interrupts, read the
GPIOn_IN_EN register and save the state prior to setting the register to 0.
2. Clear pending interrupts by writing 1 to the GPIOn_INT_CLR[pin] bit.
3. Configure the pin for the desired interrupt event
4. Set GPIOn_INT_MODE[pin] to select the desired interrupt.
a. For level triggered interrupts, the interrupt triggers on an input high (GPIOn_INT_POL[pin] = 0) or input low
level.
b. For edge triggered interrupts, the interrupt triggers on a transition from low to high(GPIOn_INT_POL[pin] = 0)
or high to low (GPIOn_INT_POL[pin] = 1).
5. Optionally set GPIOn_INT_DUAL_EDGE [pin] to 1 to trigger on both the rising and falling edges of the input signal.
6. Set GPIOn_INT_EN[pin] to 1 to enable the interrupt for the pin.
6.3.1 GPIO Interrupt Handling
Each GPIO port is assigned its own dedicated interrupt vector as shown in Table 6-6: MAX32665—MAX32668 GPIO Port
Interrupt Vector Mapping.
To handle GPIO interrupts in your interrupt vector handler, complete the following steps:
1. Read the GPIOn_INT_STAT register to determine the GPIO pin that triggered the interrupt.
2. Complete interrupt tasks associated with the interrupt source pin (application defined).
3. Clear the interrupt flag in the GPIOn_INT_STAT register by writing a 1 to the GPIOn_INT_CLR bit position that
triggered the interrupt. This also clears and rearms the edge detectors for edge triggered interrupts.
4. Signal an end-of-interrupt to the interrupt controller by writing to the End-of-Interrupt register.
5. Return from the interrupt vector handler.
6.3.2 Using GPIO for Wakeup from Low Power Modes
Low-power modes support an asynchronous wakeup from edge triggered interrupts on the GPIO ports. Level triggered
interrupts are not supported for wakeup because the system clock must be active to detect levels.
A single wakeup interrupt vector, GPIOWAKE_IRQHandler, is assigned for all pins of all GPIO ports. When the GPIO wakeup
event occurs, the application software must interrogate each GPIOn_INT_STAT register to determine which external port
pin caused the wake-up event.
Table 6-7: MAX32665―MAX32668 GPIO Wakeup Interrupt Vector
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