Maxim Integrated MAX32665 - Table 8-88: SDHC ADMA Error Status Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 217 of 457
Force Event Register for Error Interrupt Status
SDHC_FORCE_EVENT_INT_STAT
[0x0052]
Bits
Name
Access
Reset
Description
11:10
-
R/W
0
Reserved for Future Use
Do not modify this field.
9
adma
R/W
0
Force Event for ADMA Error
1: Interrupt is generated
0: No interrupt generated
8
auto_cmd
R/W
0
Force Event for Auto CMD Error
1: Interrupt is generated
0: No interrupt generated
7
curr_limit
R/W
0
Force Event for Current Limit Error
1: Interrupt is generated
0: No interrupt generated
6
data_end_bit
R/W
0
Force Event for Data End Bit Error
1: Interrupt is generated
0: No interrupt generated
5
data_crc
R/W
0
Force Event for Data CRC Error
1: Interrupt is generated
0: No interrupt generated
4
data_to
R/W
0
Force Event for Data Timeout Error
1: Interrupt is generated
0: No interrupt generated
3
cmd_index
R/W
0
Force Event for Command Index Error
1: Interrupt is generated
0: No interrupt generated
2
cmd_end_bit
R/W
0
Force Event for Command End Bit Error
1: Interrupt is generated
0: No interrupt generated
1
cmd_crc
R/W
0
Force Event for Command CRC Error
1: Interrupt is generated
0: No interrupt generated
0
cmd_to
R/W
0
Force Event for Command Timeout Error
1: Interrupt is generated
0: No interrupt generated
Table 8-88: SDHC ADMA Error Status Register
ADMA Error Status Register
SDHC_ADMA_ER
[0x0054]
Bits
Name
Access
Reset
Description
7:3
-
RO
0
Reserved for Future Use
Do not modify this field.