Maxim Integrated MAX32665 - Table 8-71: SDHC Timeout Control Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 201 of 457
Table 8-71: SDHC Timeout Control Register
Timeout Control Register
SDHC_TO
[0x002E]
Bits
Name
Access
Reset
Description
7:4
-
R/W
0
Reserved for Future Use
Do not modify this field.
3:0
data_count_value
R/W
0
Data Timeout Counter Value
Determines the interval for DAT line timeout detection. The timeout clock
frequency is generated by dividing PCLK by the value calculated using this register.
See Capabilities 0 Register (SDHC_CFG_0) for the definition of TMCLK.
The calculation for Data Timeout is shown in the following equation:
DataTimeout TMCLK  2
󰇛
13datacountvalue
󰇜
Setting
Data Timeout
0b1111
Reserved
0b1110
TMCLK  2
󰇛
27
󰇜
0b1101
TMCLK  2
󰇛
26
󰇜
…
…
0b0010
TMCLK  2
󰇛
15
󰇜
0b0001
TMCLK  2
󰇛
14
󰇜
0b0000
TMCLK  2
󰇛
13
󰇜
Note: Disable the Data Timeout Error Status Enable in the Error Interrupt Status
Enable register (SDHC_ER_INT_EN.data_to).