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Maxim Integrated MAX32665 User Manual

Maxim Integrated MAX32665
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MAX32665-MAX32668 User Guide
Maxim Integrated Page 297 of 457
I2C Interrupt Flag 0
I2Cn_INT_FL0
[0x0008]
Bits
Field
Access
Reset
Description
5
txthi
RO
1
TX FIFO Threshold Level Interrupt Flag
This field is set by hardware if the number of bytes in the Transmit FIFO is less than
or equal to the Transmit FIFO threshold level. Write 1 to clear. This field is
automatically cleared by hardware when the TX FIFO contains fewer bytes than the
TX threshold level.
0: TX FIFO contains more bytes than the TX threshold level.
1: TX FIFO contains TX threshold level or fewer bytes (Default).
4
rxthi
R/W1C
1
RX FIFO Threshold Level Interrupt Flag
This field is set by hardware if the number of bytes in the Receive FIFO is greater
than or equal to the Receive FIFO threshold level. This field is automatically cleared
when the RX FIFO contains fewer bytes than the RX threshold setting.
0: RX FIFO contains fewer bytes than the RX threshold level.
1: RX FIFO contains at least RX threshold level of bytes (Default).
3
ami
R/W1C
0
Slave Mode Incoming Address Match Status Interrupt Flag
Write 1 to clear. Writing 0 has no effect.
0: Slave address match has not occurred.
1: Slave address match occurred.
2
gci
R/W1C
0
Slave Mode General Call Address Match Received Interrupt Flag
Write 1 to clear. Writing 0 has no effect.
0: General call address match has not occurred.
1: General call address match occurred.
1
irxmi
R/W1C
0
Interactive Receive Mode Interrupt Flag
Write 1 to clear. Writing 0 is ignored.
0: Interrupt condition has not occurred.
1: Interrupt condition occurred.
0
donei
R/W1C
0
Transfer Complete Interrupt Flag
This flag is set for both Master and Slave mode once a transaction completes. Write 1
to clear. Writing 0 has no effect.
0: Transfer is not complete.
1: Transfer complete.
Table 13-9: I
2
C Interrupt Enable 0 Register
I2C Interrupt Enable 0
I2Cn_INT_EN0
[0x000C]
Bits
Field
Access
Reset
Description
31:24
-
RO
0
Reserved
23
wramie
R/W
0
Slave Write Address Match Interrupt Enable
This bit is set to enable interrupts when the device is accessed in slave mode and the
address received matches the device slave addressed for a write transaction.
0: Disabled.
1: Enabled.
22
rdamie
R/W
0
Slave Read Address Match Interrupt Enable
This bit is set to enable interrupts when the device is accessed in slave mode and the
address received matches the device slave addressed for a read transaction.
0: Disabled.
1: Enabled.
21:16
-
RO
0
Reserved
15
txloie
R/W
0
TX FIFO Lock Out Interrupt Enable
0: Disabled.
1: Enabled.

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Maxim Integrated MAX32665 Specifications

General IconGeneral
BrandMaxim Integrated
ModelMAX32665
CategoryMotherboard
LanguageEnglish