Maxim Integrated MAX32665 - Table 2-8: RPU AHB Slave Permission Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 33 of 457
Register Name
Register Mnemonic
Reference
I2C 0 (Bus 1) RPU Register
I2C0_BUS1
See Table 2-5
I2C 1 (Bus 1) RPU Register
I2C1_BUS1
See Table 2-5
I2C 2 (Bus 1) RPU Register
I2C2_BUS1
See Table 2-5
Pulse Train Engine (Bus 1) RPU Register
PTG_BUS1
See Table 2-5
Bits
Name
Access
Reset
Description
31:0
access
R/W
0
APB Slave Peripheral Access Disable
0: AHB master read/write access allowed
1: AHB master read/write access denied
This field allows or denies access to the peripheral by one or more AHB masters as shown
in Table 2-2. Unused bits should not be changed from their reset default values
Table 2-8: RPU AHB Slave Permission Register
Register Name
Register Mnemonic
Reference
USB Endpoint Data RPU Register
USBHS
See Table 2-6
SDIO/SDHC Target Memory RPU Register
SDIO/SDHC Target
See Table 2-6
SPI Bus Master FIFO RPU Register
SPIM
See Table 2-6
QSPI Data Buffer RPU Register
QSPI/SPI
See Table 2-6
System RAM, Memory Instance 0
SYS_RAM (MI0)
See Table 2-6
System RAM, Memory Instance 1
SYS_RAM (MI1)
See Table 2-6
System RAM, Memory Instance 2
SYS_RAM (MI2)
See Table 2-6
System RAM, Memory Instance 3
SYS_RAM (MI3)
See Table 2-6
System RAM, Memory Instance 4
SYS_RAM (MI4)
See Table 2-6
System RAM, Memory Instance 5
SYS_RAM (MI5)
See Table 2-6
System RAM, Memory Instance 6
SYS_RAM (MI6)
See Table 2-6
Bits
Name
Access
Reset
Description
31:0
access
R/W
0
AHB Slave Peripheral Access Disable
0b00: AHB master write/read access allowed
0b01: AHB master write access allowed / read access denied
0b10: AHB master write access denied / read access allowed
0b11: AHB master write/read access denied
Each bit pair of this field allows or denies access to the peripheral by one or more AHB
masters as shown in Table 2-2. Unused bits should not be changed from their reset
default values.