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Maxim Integrated MAX32665 - Table 8-47: SDHC SDMA Block Size Register

Maxim Integrated MAX32665
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MAX32665-MAX32668 User Guide
Maxim Integrated Page 187 of 457
Table 8-47: SDHC SDMA Block Size Register
SDMA Block Size Register
SDHC_BLK_SIZE
[0x0004]
Bits
Name
Access
Reset
Description
31:15
-
R/W
0
Reserved for Future Use
Do not modify this field.
14:12
host_buf
R/W
0
Host SDMA Buffer Size
This field specifies the size of the contiguous buffer in the system memory for SDMA
transfers. SDMA transfers larger than this buffer generates a SDHC DMA interrupt
(SDHC_INT_STAT.dma) when the transfer reaches the host_buf size boundary. The
SDMA transfer pauses until the card driver updates the SDMA System Address
(SDHC_SDMA) register with the next buffer address to transfer and clears the SDHC
DMA interrupt flag. When the SDMA transfer is complete, a SDHC transfer complete
interrupt (SDHC_INT_STAT.trans_comp = 1) is generated. The SDHC DMA interrupt
flag is not set when the SDMA transfer completes.
host_buf
Value
Host SDMA
Buffer Size (KB)
0b000
4
0b001
8
0b010
16
0b011
32
0b100
64
0b101
128
0b110
256
0b111
512
Note: This field is used for SDMA transfers only.
11:0
trans
R/W
0x0200
Data Transfer Block Size
Sets the block size of data transfers for CMD17, CMD18, CMD24, CMD25, and CMD53.
You can set values ranging from 1 up to the maximum buffer size. Setting this field to
0 indicates there is no data to transfer.
During a transfer, reading this field might return an invalid value, and writes to this
field are ignored.
trans Value
Block Size in
Bytes
0x0800
2,048
0x07FF
2,047
...
...
0x200
512
0x01FF
511
...
...
0x0004
4
0x0003
3
0x0002
2
0x0001
1
0x0000
No data transfer

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