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Maxim Integrated MAX32665 - Isochronous out Endpoints; Table 21-4: USB Isochronous out Endpoint Options

Maxim Integrated MAX32665
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MAX32665-MAX32668 User Guide
Maxim Integrated Page 408 of 457
Isochronous IN Endpoint Option
Description
Error Handling
If an Isochronous IN endpoint receives an IN Token while the IN FIFO is empty, it creates an
underrun condition. This automatically sets the USBHS_INCSRL.underrun bit and results in the
USBHS sending a null packet to the USB Host.
If firmware is loading the IN Endpoint FIFO one packet per frame, it should check that there is room
in the IN FIFO by making sure the USBHS_INCSRL.inpktrdy bit is cleared before loading the next
packet. If this bit is set, it indicates that a data packet is still in the FIFO and has not been sent,
possibly from a corrupt IN Token. This error condition must be handled by firmware, for example,
firmware might flush the unsent packet, or skip the current packet.
Error Handling High Bandwidth
Isochronous IN Endpoints Only
High-bandwidth Isochronous IN endpoints can transfer three 1024-byte packets in one payload. To
the USB bus, it appears to be a single packet of 3072 bytes with a data transfer rate of up to
24MBps. If a high-bandwidth isochronous data transfer is split into more than one packet but has
not received enough IN tokens from the Host to send all the packets, an error condition exists. In
this case, the Incomplete Split Transfer Error Status bit USBHS_INCSRL.incomPTn, is automatically
set. This also automatically flushes the remainder of the packet from the IN FIFO. If a second
packet is in the IN FIFO, it is not flushed. Because the packet was lost, the USBHS_INCSRL.inpktrdy
bit is cleared.
21.10.2 Isochronous OUT Endpoints
An Isochronous OUT endpoint is used to transfer time-sensitive but loss-tolerant data from the Host to the function
controller. Five optional features are available for use with an Isochronous OUT endpoint as shown in Table 21-4.
Table 21-4: USB Isochronous OUT Endpoint Options
Isochronous OUT Endpoint Option
Description
Double Packet Buffering
When the value written to the USBHS_OUTMAXP register is less than or equal to half the size of
the FIFO allocated to the endpoint, and double packet buffering is allowed
(USBHS_OUTCSRU.dpktbufdis = 0), double packet buffering is enabled. This allows the storage of
up to two packets in the FIFO for transmission to the Host. Double packet buffering is
recommended for isochronous OUT endpoints to avoid data overrun errors.
DMA Transfers
If the DMA is enabled for an endpoint, a DMA request is generated whenever the endpoint can
accept another full packet in its FIFO. However, there is little benefit with Isochronous endpoints
because the packets transferred are often not the maximum packet size. In this situation, the
USBHS_INCSRL.underrun bit would need to be checked for underrun errors after each packet.
AutoClear
When the AutoClear feature is enabled (USBHS_OUTCSRU.autoclear = 1), the
USBHS_OUTCSRL.outpktrdy bit is automatically cleared when a packet of USBHS_OUTMAXP bytes
is unloaded from the FIFO. However, there is little benefit with Isochronous endpoints because the
packets transferred are often not the maximum packet size. In this situation, the
USBHS_INCSRL.underrun bit would need to be checked for underrun errors after each packet.
Error Handling
If a packet is received from a USB Host, but the OUT FIFO is full, it creates an overrun error
condition. The register bit USBHS_OUTCSRL.overrun is automatically set. This error condition
usually means that firmware is not unloading the OUT FIFO fast enough. This error condition must
be handled by firmware.
If a received packet has a CRC error the packet is stored in the OUT FIFO, and both the
USBHS_OUTCSRL.dataerror bit and the USBHS_OUTCSRL.outpktrdy bit are set. This error condition
must be handled by firmware.

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