MAX32665-MAX32668 User Guide
Maxim Integrated Page 432 of 457
The setting of the read and write FIFOs sources are detailed in each section of specific operations.
For cipher, hash, or Galois operations most operations are finished when the DMA transfer is complete. If the
CRYPTO_CTRL.rdsrc is configured for DMA, both the CRYPTO_CTRL.dma_done and the associated .done flag are set after the
entire DMA operation is complete. In most cases only the CRYPTO_CTRL.done flag is required. Setting the
CRYPTO_CTRL.dmadnemsk field will prevent the CRYPTO_CTRL.dma_done field from setting the CRYPTO_CTRL.done bit.
This reduces software overhead by only using the specific operation’s .done flag and masking the DMA from interrupting
the CPU.
For cipher operations, when CRYPTO_CTRL.wrsrc is configured for cipher output, the CRYPTO_CTRL.cph_done is set only
after the last cipher text has completed the DMA transfer out to memory.
After the cryptographic accelerator reset, the CRYPTO_CTRL.rdy must be polled in the software before any other actions
can start.
23.1.2 Direct FIFO Access
The read and write FIFOS are directly accessible via the CRYPTO_DIN_[3:0] and CRYPTO_DOUT_[3:0] registers, respectively.
In general, however, the CMDA is much more efficient and requires less interaction.
If direct access is required, only 32-bit accesses to the CRYPTO_DIN_0 and CRYPTO_DOUT_0 registers should be used. Do
not use the registers [3:1] for direct access.
23.1.3 Cache Security
Cryptographic operands and results may be stored in cached memory as part of normal device operation. For increased
security, invalidate the cache memory associated with memory used in cryptographic operations.
23.2 Block Cipher Accelerator
The block cipher accelerator is a dedicated hardware module that accelerates the computation of the following algorithms:
• AES-128
• AES-192
• AES-256
• Data Encryption Standard (DES)
• Triple Data Encryption Algorithm (TDEA/3DES)
• DES and TDEA have been deprecated by NIST are only provided for legacy support.
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