Maxim Integrated MAX32665 - Table 8-10. SPIXF Controller Interrupt Status Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 156 of 457
SPIXF Controller Special Control Register
SPIXFC_SP_CTRL
[0x0010]
Bits
Name
Access
Reset
Description
3:1
-
R/W
0
Reserved for Future Use
Do not modify this field
0
sampl
R/W
0
SDIO Sample Mode Enable
Setting this bit to a 1 enables the ability to drive SDIO outputs prior to the
assertion of Slave Select. This bit must only be set when the SPIXF bus is idle and
the transmit FIFO is empty. This bit is automatically cleared by hardware after
the next slave select assertion.
0: Sample Mode disabled
1: Sample mode enabled
Table 8-10. SPIXF Controller Interrupt Status Register
SPIXF Controller Interrupt Status Register
SPIXFC_INT_FL
[0x0014]
Bits
Name
Access
Reset
Description
31:6
-
R/W1C
0
Reserved for Future Use
Do not modify this field.
5
rfifoaf
R/W1C
0
Receive FIFO Almost Full Flag.
This flag is set by hardware when the Receive FIFO is almost full as defined by
SPIXFC_FIFO_CTRL.rfifolvl.
0: Receive FIFO level below the Almost Full level
1: Receive FIFO level at almost full level.
4
tfifoae
R/W1C
1
Transmit FIFO Almost Empty Flag.
This flag is set by hardware when the Transmit FIFO is almost empty as defined
by SPIXFC_FIFO_CTRL.tfifolvl. This does not depend on block enable or the slave
select value.
0: Transmit FIFO not Almost Empty
1: Transmit FIFO Almost Empty.
3
rdone
R/W1C
0
Receive Done Interrupt Status.
This flag is set by hardware when the Receive FIFO is not empty, and the slave
select is deasserted.
0: Receive FIFO ready
1: Receive FIFO Not ready.
2
trdy
R/W1C
0
Transmit Ready Interrupt Status.
This flag is set by hardware when the Transmit FIFO is empty, and the slave
select is deasserted.
0: Transmit FIFO not ready
1: Transmit FIFO is ready.
1
rstall
R/W1C
0
Receive Stalled Interrupt Flag.
This flag is set by hardware when the Receive FIFO is full, and the selected slave
select is asserted.
0: Normal FIFO operation.
1: Stalled FIFO.