Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 178 of 457
SPIXR External Memory Control Register
SPIXR_XMEM_CTRL
[0x0034]
Bits
Name
Access
Reset
Description
15:8
xmem_wr_cmd
R/W
0
Write command to be received at the external memory
Vendor specific value
7:0
xmem_rd_cmd
R/W
0
Read command to be received at the external memory
Vendor specific value
8.4 SPIXR Cache Controller (SRCC)
The SPIXR Cache Controller is an AHB block that has multiple interfaces. The address and data interface is connected to the
AHB and the SRCC register interface is connected via the APB.
The SRCC is a 16KB 2-way set-associative cache. It operates with the LRU replacement policy and has write-through
implementation used for caching instructions and data from an external SPI-XiP RAM device. The SRCC includes tag RAM,
cache RAM and a line fill buffer as shown in Figure 4-6: MAX32665—MAX32668 Cache Controllers Control. Write allocate
and critical word first are options controlled by the application. Each cache line is 256-bits wide with the lower 5-bits of the
address used as the cache line index. The SRCC uses tag cache RAM with 8-bits of the address index and a 5-bit line offset to
access the tag cache RAM. 16-bits of the address are stored in tag RAM for hit/miss checking enabling the SRCC to access up
to 512MB of external memory. The SRCC interfaces to the address range of 0x8000 0000 to 0x9FFF FFFF for a maximum of
512MB external.
8.4.1 Features
• 2-way set associative, LRU (Least-Recently Used) replacement policy
• Write-no-allocate with option to Write-allocate
• Write-through
• Read critical word first and streaming
• 512MB addressable range
• 16KB size
8.4.2 Enabling the SRCC
Enable the SRCC as follows:
1. Set the GCR_SCON.dcache_dis field to 0.
2. Set the SRCC_CACHE_CTRL.enable field to 1.
Once enabled, the cache is empty and begins filling when a read from or write to (if write allocate is enabled) the external
memory is performed.
After a Power-On-Reset event, the cache tag RAM is cleared by hardware ensuring that no corrupted data is accessed from
the initial cache read.
8.4.3 Disabling the SRCC
Disabling the SRCC cache automatically invalidates the cache contents. All access to the external memory while the SRCC
cache is disabled are performed using the Line Buffer.
Disable the SRCC by setting SRCC_CACHE_CTRL.enable to 0.
The SRCC cache and Line Buffer can both be bypassed by setting GCR_SCON.dcache_dis to 1. Bypassing the SRCC enables
direct access to the external memory from the application firmware.

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English