Maxim Integrated MAX32665 - Table 13-7: I C Status Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 294 of 457
I2C Control 0
I2Cn_CTRL0
[0x0000]
Bits
Field
Access
Reset
Description
9
sda
R
-
SDA Status
0: SDA pin is logic low.
1: SDA pin is logic high.
8
scl
R
-
SCL Status
0: SCL pin is logic low.
1: SCL pin is logic high.
7
sdao
R/W
0
SDA Pin Output Control
Set the state of the SDA hardware pin (actively pull low or float).
0: Pull SDA Low
1: Release SDA
Note: Only valid when I2Cn_CTRL0.swoe=1
6
sclo
R/W
0
SCL Pin Output Control
Set the state of the SCL hardware pin (actively pull low or float).
0: Pull SCL low
1: Release SCL
Note: Only valid when I2Cn_CTRL0.swoe=1
5
-
RO
0
Reserved
4
ack
R/W
0
Interactive Receive Mode (IRXM) Acknowledge
If IRXM is enabled (I2Cn_CTRL0.irxm = 1), this field determines if the hardware sends
an ACK or a NACK to an IRM transaction.
0: Respond to IRXM with ACK
1: Respond to IRXM with NACK
3
irxm
R/W
0
Interactive Receive Mode (IRXM)
When receiving data, allows for an Interactive Receive Mode (IRM) interrupt event
after each received byte of data. The I
2
C peripheral hardware can be enabled to send
either an ACK or NACK for IRXM. See Interactive Receive Mode section for detailed
information.
0: Disable
1: Enable
Note: Only set this field when the I
2
C bus is inactive.
2
gcen
R/W
0
General Call Address Enable
0: Ignore General Call Address
1: Acknowledge General Call Address
1
mst
R/W
0
Master Mode Enable
0: Slave mode enabled.
1: Master mode enabled.
0
i2cen
R/W
0
I
2
C Peripheral Enable
0: Disabled
1: Enabled
Table 13-7: I
2
C Status Register
I2C Status
I2Cn_STAT
[0x0004]
Bits
Field
Access
Reset
Description
31:6
-
RO
0
Reserved