Maxim Integrated MAX32665 - Registers; Register Details; Table 15-1. Htimer Registers Summary; Table 15-2: Htimer Long-Interval Counter Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 326 of 457
15.4 Registers
See Table 3-1: APB Peripheral Base Address Map for the HTimer Register Peripheral Base Addresses. All fields are reset on
peripheral, system, or power-on reset events unless otherwise specified.
Table 15-1. HTimer Registers Summary
Offset
Register
Description
[0x0000]
HTIMER_SEC
HTimer Long-Interval Counter Register
[0x0004]
HTIMER_SSEC
HTimer Short-Interval Counter Register
[0x0008]
HTIMER_RAS
HTimer Long-Interval Alarm Register
[0x000C]
HTIMER_RSSA
HTimer Short-Interval Alarm Register
[0x0010]
HTIMER_CTRL
HTimer Control Register
15.5 Register Details
Table 15-2: HTimer Long-Interval Counter Register
HTimer Long-Interval Counter
HTIMER_SEC
[0x0000]
Bits
Field
Access
Reset
Description
31:0
rts
R/W
-
Long-Interval Counter
This register increments each time HTIMER_SSEC.rtss rolls over.
Table 15-3: HTimer Short-Interval Counter Register
HTimer Short-Interval Counter
HTIMER_SSEC
[0x0004]
Bits
Field
Access
Reset
Description
31:8
-
R/W
0
Reserved
7:0
rtss
R/W
-
Short-Interval Counter
This register increments once per t
HTCLK
tick.
Table 15-4: HTimer Long-Interval Alarm Register
HTimer Long-Interval Alarm
HTIMER_RAS
[0x0008]
Bits
Field
Access
Reset
Description
31:20
-
R/W
0
Reserved for Future Use
Do not modify this field from its default value.
19:0
ras
R/W
0
Long-Interval Alarm
Sets the long-interval alarm. A system interrupt is generated when
HTIMER_SEC.rts[19:0] matches HTIMER_RAS.ras.
Table 15-5: HTimer Short-Interval Alarm Register
HTimer Short-Interval Alarm
HTIMER_RSSA
[0x000C]
Bits
Field
Access
Reset
Description
31:0
rssa
R/W
0
Short-Interval Alarm
Sets the starting and reload values for the short-interval alarm.