Maxim Integrated MAX32665 - Register Access Control; Register Write Protection; Register Read Protection; Count Register Access

MAX32665-MAX32668 User Guide
Maxim Integrated Page 325 of 457
15.3 Register Access Control
The hardware provides a collision-protection mechanism that prevents software from reading registers at the same time
they are being updated by hardware, and vice versa.
15.3.1 Register Write Protection
The HTIMER_CTRL.busy bit is a read-only status bit controlled by hardware and set when any of the following conditions
occur:
• System Reset.
• Software writes to the HTIMER_SEC.rts.
• Software modifies the HTIMER_CTRL.enable, HTIMER_CTRL.alarm_tod_en, or HTIMER_CTRL.alarm_ss_en bits.
When the HTIMER_CTRL.busy bit is set by hardware, writes to the above bits and count registers are blocked by hardware.
The HTIMER_CTRL.busy bit remains active until the register or bit is synchronized by hardware. The synchronization by
hardware occurs on the next timer tick. The HTIMER_CTRL.busy bit is set for a maximum of one timer tick. Therefore, a
software write is not complete until hardware clears the HTIMER_CTRL.busy bit.
Once the HTIMER_CTRL.busy bit is cleared to 0, additional writes are completed as permitted by individual count or alarm-
enable bits.
15.3.2 Register Read Protection
The HTIMER_CTRL.ready bit indicates when the count registers contain valid data. Hardware clears the HTIMER_CTRL.ready
bit approximately one timer tick before the ripple occurs through the counter registers (HTIMER_SEC.rts and HTIMER_SSEC)
and is set once again immediately after the ripple occurs. The period of the HTIMER_CTRL.ready bit set/clear activity
provides a large window during which the counter registers are readable. Software can clear the HTIMER_CTRL.ready bit at
any time and the bit remains clear until set by hardware when the next ripple occurs. A separate Ready Enable
(HTIMER_CTRL.ready_int_en) bit is provided to generate an interrupt when hardware sets the HTIMER_CTRL.ready bit. You
can use this interrupt to signal the start of a new timer read window.
15.3.3 Count Register Access
Values read from the count registers (HTIMER_SEC.rts and HTIMER_SSEC) are valid only when the HTIMER_CTRL.ready = 1.
To write the count registers, disable the timer by clearing (HTIMER_CTRL.enable) to 0. Clearing the HTIMER_CTRL.enable bit
is permitted only when the Write Enable (HTIMER_CTRL.write_en) bit is set to 1 and is governed by the HTIMER_CTRL.busy
bit signaling process (that is, the HTIMER_CTRL.busy bit is 0). Writes to each count register must occur only when the
HTIMER_CTRL.busy bit reads 0.
15.3.4 Alarm Register Access
The alarm registers HTIMER_RAS and HTIMER_RSSA are readable at any time.
Set HTIMER_CTRL.alarm_ss_en = 0 before writing to HTIMER_RSSA.rssa. Set HTIMER_CTRL.alarm_tod_en = 0 before writing
to HTIMER_RAS.
Clearing these bits requires monitoring the HTIMER_CTRL.busy bit to assess completion of the write. Once the alarm is
disabled, update the associated alarm registers using software.