Maxim Integrated MAX32665 - Table 8-33. SPIXR Interrupt Enable Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 175 of 457
SPIXR Interrupt Status Flag Register
SPIXR_INT_FL
[0x0020]
Bits
Name
Access
Reset
Description
8
fault
R/W1C
0
Multi-Master Fault Flag
Set if the SPI is in Master Mode, Multi-Master Mode is enabled, and a Slave
Select input is asserted. A collision also sets this flag.
7:6
-
R/W1C
0
Reserved for Future Use
Do not modify this field.
5
ssd
R/W1C
0
Slave Select Deasserted Flag
4
ssa
R/W1C
0
Slave Select Asserted Flag
3
rx_full
R/W1C
0
RX FIFO Full Flag
Set when the RX FIFO is full.
2
rx_level
R/W1C
0
RX FIFO Threshold Level Crossed Flag
Set when the RX FIFO exceeds the value in SPIXR_DMA.rx_fifo_level.
1
tx_empty
R/W1C
1
TX FIFO Empty Flag
Set when the TX FIFO is empty.
0
tx_level
R/W1C
0
TX FIFO Threshold Level Crossed Flag
Set when the TX FIFO is less than the value in SPIXR_DMA.tx_fifo_level.
Table 8-33. SPIXR Interrupt Enable Register
SPIXR Interrupt Enable Register
SPIXR_INT_EN
[0x0024]
Bits
Name
Access
Reset
Description
31:16
-
R/W
0
Reserved for Future Use
Do not modify this field.
15
rx_und
R/W
0
RX FIFO Underrun Interrupt Enable
1: Interrupt enabled
0: Interrupt disabled
14
rx_ovr
R/W
0
RX FIFO Overrun Interrupt Enable
1: Interrupt enabled
0: Interrupt disabled
13
tx_und
R/W
0
TX FIFO Underrun Interrupt Enable
1: Interrupt enabled
0: Interrupt disabled
12
tx_ovr
R/W
0
TX FIFO Overrun Interrupt Enable
1: Interrupt enabled
0: Interrupt disabled
11
m_done
R/W
0
Master Data Transmission Done Interrupt Enable
1: Interrupt enabled
0: Interrupt disabled
10
-
R/W
0
Reserved for Future Use
Do not modify this field.
9
abort
R/W
0
Slave Mode Transaction Abort Detected Interrupt Enable
1: Interrupt enabled
0: Interrupt disabled