MAX32665-MAX32668 User Guide
Maxim Integrated Page 179 of 457
8.4.4 SRCC Registers
See Table 3-1: APB Peripheral Base Address Map for the SRCC Peripheral Base Address.
Table 8-38: External Memory Cache Controller Register Addresses and Descriptions
Cache Memory Size Register
8.4.5 SRCC Register Details
Table 8-39: SRCC Cache ID Register
Reserved for Future Use
Do not modify this field.
Cache ID
Returns the Cache ID for this Cache instance.
Cache Part Number
Returns the part number indicator for this Cache instance.
Cache Release Number
Returns the release number for this Cache instance.
Table 8-40: SRCC Memory Size Register
SRCC Memory Size Register
Addressable Memory Size
Indicates the size of addressable memory by this cache controller instance in
128KB units.
Cache Size
Returns the size of the cache RAM memory in 1KB units.
16: 16KB Cache RAM
Table 8-41: SRCC Cache Control Register
SRCC Cache Control Register
Reserved for Future Use
Do not modify this field.
Ready
This field is cleared by hardware anytime the cache as a whole is invalidated
(including a Power-On Reset event). Hardware automatically sets this field to 1
when the invalidate operation is complete and the cache is ready.
0: Cache Invalidate in process.
1: Cache is ready.
Note: While this field reads 0, the cache is bypassed and reads come directly from
the line fill buffer.
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