MAX32665-MAX32668 User Guide
Maxim Integrated Page 36 of 457
Figure 3-2: Data Memory Mapping
Undefined
0x0000_0000
0x0FFF_FFFF
Data Read Access to Code Space
(Not cached)
0x1000_0000
0x102F_FFFF
Reserved
0x1030_0000
0x1FFF_FFFF
0x0800_0000
0x07FF_FFFF
Read/Write Access To Data in
SRAM
(Not cached)
0x2000_0000
Reserved
0xFFFF_FFFF
D-Code A HB Bus Master
System AHB Bus Master
Legend
ARM Cort ex-M4 AHB Bus Mast ers
Memory Spaces AHB Bus Slaves
External Memory Device (Optional)
Undefined/Reserve d
0x3FFF_FFFF
0xA000_0000
Reserved
Read/Write Access To Peripheral
Space (Not cached)
0x4000_0000
0x5FFF_FFFF
External SPI Flash
Memory (QSPI SPIXF,
128MB Maximum)
SRAM
560KB (no ECC)
448KB (with ECC)
0x0FFF_FFFF
0x0800_0000
0x2000_0000
0x2008_BFFF
USB 2.0 High Speed
Reserved
SD/SDIO/SDHC/MMC
Controller
Reserved
SPIXF Master Controller
FIFO
Reserved
SPI0
Global Control Registers
SI Registers
Function Control Registers
Reserved
TPU, AES, MAA, SHA
RPU
Watch dog Timer (0, 1, 2)
Security Monitor
SIMO Controller
AES K eys
Reserved
RTC
Wake-Up Timer
Power Sequencer
GPIO Po rt 0
GPIO Po rt 1
Reserved
Timer (0, 1, 2, 3, 4, 5)
HTimer 1
HTimer 0
I2C (0, 1, 2) BUS 0
Reserved
SPIXF Master
SPIXF M aster Controller
Standard DMA 0
Flash Controller 1
Flash Controller 0
I-Cache Controller 0
Reserved
SPIXR Cache Controller
ADC
Smart DMA
Reserved
Reserved
SPIXR Master Controller
Reserved
Pulse Trains - BUS 0
1-Wire
Semaphores
Reserved
UART (0, 1, 2)
Reserved
SPI (1,2)
0x4000_0000
0x4000_0000
AHB-to-APB B ridge (APB
Register Modules)
Reserved
0x4000_0400
0x4000_0800
0x4000_0C00
0x4000_1000
0x4000_2000
0x4000_3000
0x4000_4000
0x4000_4400
0x4000_5000
0x4000_5400
0x4000_6000
0x4000_6400
0x4000_6800
Misc. Control Registers0x40 00_6C00
0x4000_8000
0x4000_9000
0x4000_A000
0x4001_0000
0x4001_B000
0x40 01_C000
0x40 01_D000
0x4002_0000
0x4002_6000
0x4002_7000
0x4002_8000
0x4002_9000
0x4002_9400
0x4002_A000
0x4002_A800
SPIXF Cache Controller0x4002_F000
Reserved0x4003_0000
0x4003_3000
0x4003_4000
Standard DMA 10x4003_5000
0x4003_6000
0x4003_7000
0x4003_8000
0x4003_A000
0x4003_B000
0x4003_C000
0x40 03_D000
0x4003_E000
0x4003_F000
0x4004_2000
0x4004_5000
0x4004_6000
0x400B_0000
0x400B_1000
0x400B_2000
0x400B_6000
0x400B_7000
0x400B_C000
0x400B_D000
0x400B_E000
APB B us Registe r Module
Standard DMA, S mart DMA AHB Bus Masters
SD/SDI O/SDHC/MMC, US B, TPU/TRNG AHB Bus M asters
AHB Bus Masters
Internal Memory Instances
DVS Controller
Reserved
0x4000_4800
0x40 00_4C00
Reserved0x4000_7000
I-Cache Controller 1
0x4002_A400
Reserved0x4004_8000
Audio Subsystem
TRNG
Reserved
0x4004_C000
0x40 04_D000
0x4004_E000
BLE Registers and IQ RAMs0x4005_0000
Reserved0x4006_0000
I2C (0, 1, 2) BUS 1
Reserved
0x40 11_D000
0x4012_0000
Pulse Trains - BUS 10x40 13_C000
0x2006_FFFF
0x2007_0000
0x2008_BFFF
Ext. SPI SRAM
(QSPI SPIXR, 512MB
Maximum)
0x8000_0000
0x9FFF_FFFF
Int. Program/Data Flash
512KB (Block 0) + ECC
0x1000_0000
0x100F_FFFF
0x1007_FFFF
0x1008_0000
Int. Program/Data Flash
512KB (Block 1) + ECC
Information Block 1
Iformation Block 0
0x1080_0000
0x1080_3FFF
0x1080_4000
0x1080_7FFF
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