Maxim Integrated MAX32665 - Table 9-13: Dmachn Source Register

MAX32665-MAX32668 User Guide
Maxim Integrated Page 235 of 457
DMA Channel n Status
DMACHn_ST
[0x0104]
Bits
Field
Access
Reset
Description
6
to_st
R/W1C
0
Timeout Status
Timeout status field. Write 1 to clear.
0: No time out.
1: A channel time out has occurred
5
-
RO
0
Reserved
4
bus_err
R/W1C
0
Bus Error
If this bit reads 1, an AHB abort occurred and the channel was disabled by
hardware. Write 1 to clear.
0: No error found
1: An AHB bus error occurred
3
rld_st
R/W1C
0
Reload Status
Reload status field. Write 1 to clear.
0: Reload has not occurred.
1: Reload occurred.
2
ctz_st
R/W1C
0
CTZ Status
Write 1 to clear.
0: CTZ has not occurred.
1: CTZ has occurred.
1
ipend
RO
0
Channel Interrupt Pending
0: No interrupt
1: Interrupt pending
0
ch_st
RO
0
Channel Status
This bit indicates when it is safe to change the configuration, address, and count
registers for the channel.
Whenever this bit is cleared by hardware, the DMACHn_CFG.chen bit is also
cleared.
0: Disabled.
1: Enabled.
Table 9-13: DMACHn Source Register
DMA Channel n Source
DMACHn_SRC
[0x0108]
Bits
Field
Access
Reset
Description
31:0
src
R/W
0
Source Device Address
For peripheral transfers, the actual address field is either ignored or forced
to zero because peripherals only have one location to read/write data based
on the request select chosen.
If DMACHn_CFG.srcinc = 1, then this register is incremented on each AHB
transfer cycle by one, two, or four bytes depending on the data width.
If DMACHn_CFG.srcinc = 0, this register remains constant.
If a CTZ condition occurs while DMACHn_CFG.rlden = 1, then this register is
reloaded with the contents of the DMAn_SRC_RLD register.