Maxim Integrated MAX32665 - Page 103

MAX32665-MAX32668 User Guide
Maxim Integrated Page 103 of 457
Peripheral Clock Disable 1
GCR_PCLK_DIS1
[0x0048]
Bits
Field
Access
Reset
Description
27
wdt0
R/W
1
Watchdog Timer 0 Disable
Disabling the clock disables functionality while also saving power. Associated register
states are retained but read and write access is blocked.
0: Enabled.
1: Disabled.
26
htimer1
R/W
1
HTIMER1 Clock Disable
Disabling the clock disables functionality while also saving power. Associated register
states are retained but read and write access is blocked.
0: Enabled.
1: Disabled.
25
htimer0
R/W
1
HTIMER0 Clock Disable
Disabling the clock disables functionality while also saving power. Associated register
states are retained but read and write access is blocked.
0: Enabled.
1: Disabled.
24
i2c2
R/W
1
I
2
C2 Clock Disable
Disabling the clock disables functionality while also saving power. Associated register
states are retained but read and write access is blocked.
0: Enabled.
1: Disabled.
23
audio
R/W
1
Audio Interface Clock Disable
Disabling the clock disables functionality while also saving power. Associated register
states are retained but read and write access is blocked.
0: Enabled.
1: Disabled.
22
-
RO
1
Reserved
Do not modify this field.
21
dma1
R/W
1
DMA1 Clock Disable
Disabling the clock disables functionality while also saving power. Associated register
states are retained but read and write access is blocked.
0: Enabled.
1: Disabled.
20
spixipr
R/W
1
SPIXR Clock Disable
Disabling the clock disables functionality while also saving power. Associated register
states are retained but read and write access is blocked.
0: Enabled.
1: Disabled.
19:15
-
RO
1
Reserved
Do not modify this field.
14
spi3
R/W
1
QSPI3 Clock Disable
Disabling the clock disables functionality while also saving power. Associated register
states are retained but read and write access is blocked.
0: Enabled.
1: Disabled.