MAX32665-MAX32668 User Guide
Maxim Integrated Page 284 of 457
For slave mode operation, the following registers should be configured with the I2C peripheral disabled:
• I2Cn_CTRL0.mst – 0 for Slave operation.
• I2Cn_CTRL0.gcen
• I2Cn_CTRL0.irxm – The recommended value for this field is 0. Also, note that a setting of 1 is incompatible with
slave mode operation with clock stretching disabled (I2Cn_CTRL0.scl_strd=1).
• I2Cn_CTRL0.scl_strd
• I2Cn_CTRL0.hsmode
• I2Cn_RX_CTRL0.dnr – SMBus/PMBus applications should set this to 0, while other applications should set this to 1.
• I2Cn_TX_CTRL0.rnacktxafdis
• I2Cn_TX_CTRL0.samrtxafdis
• I2Cn_TX_CTRL0.samwtxafdis
• I2Cn_TX_CTRL0.gcamtxafdis
• I2Cn_TX_CTRL0.txpreld – Recommended value is 0 for applications that can tolerate slave clock stretching (scl_strd
= 0), and 1 for applications that do not allow slave clock stretching (scl_strd = 1).
• I2Cn_CLK_HI.scl_hi – Applies to Slave Mode when clock stretching is enabled (scl_strd=0) - This will be used to
satisfy tSU;DAT after clock stretching; program it so that the value defined by Equation 1-1 is >= tSU;DAT(min)
• I2Cn_HS_CLK.hs_clk_hi – Applies to Slave Mode when clock stretching is enabled (scl_strd=0) - This will be used to
satisfy tSU;DAT after clock stretching during Hs-Mode operation; program it so that the value defined by Equation
1-1 is >= tSU;DAT(min) for Hs-Mode
• I2Cn_SLV_ADDR.sla
• I2Cn_SLV_ADDR.ea
In contrast to the above registers, these registers can be safely (re)programmed at any time:
• All Interrupt Flags and Interrupt Enables
• I2Cn_TX_CTRL0.txth and I2Cn_RX_CTRL0.rxth – TX and RX FIFO Threshold Levels
• I2Cn_TX_CTRL1.tx_rdy – Transmit Ready (Can only be cleared by hardware)
• I2Cn_TIMEOUT.to – Time Out Control
• I2Cn_DMA.rxen/I2Cn_DMA.txen – TX and RX DMA Enables
• I2Cn_FIFO.data – FIFO access register
13.4.7.1 Slave Transmitter
The device will operate as a slave transmitter when the received address matches the device slave address with the R/W bit
set to 1. The master is then reading from the device slave. There two main modes of slave transmitter operation: just-in-
time mode and preload mode.
In just-in-time mode, firmware waits to write the transmit data to the TX FIFO until after the master addresses it for a READ
transaction, “just in time” for the data to be sent to the master. This allows firmware to defer the determination of what
data should be sent until the time of the address match. As an example, the transmit data could be based off an
immediately preceding I
2
C WRITE transaction that requests a certain block of data to be sent, or the data could represent
the latest, most up-to-date value of a sensor reading. Clock stretching must be enabled (I2Cn_CTRL0.scl_strd = 0) for just-in-
time mode operation.
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