MAX32665-MAX32668 User Guide
Maxim Integrated Page 285 of 457
Program flow for transmit operation in just-in-time mode is as follows:
1. With I2Cn_CTRL0.i2cen = 0, initialize all relevant registers, including specifically for this mode I2Cn_CTRL0.scl_strd =
0, I2Cn_TX_CTRL0[5:2] = 0x8 and I2Cn_TX_CTRL0.txpreld=0. Don't forget to program I2Cn_CLK_HI.scl_hi and
I2Cn_HS_CLK.hs_clk_hi with appropriate values satisfying tSU;DAT (and HS tSU;DAT).
2. SW sets I2Cn_CTRL0.i2cen = 1.
a. The controller is now listening for its address. For either a transmit (R/W = 1) or receive (R/W = 0) operation,
the peripheral will respond to its address with an ACK.
b. When the address match occurs, HW will set I2Cn_INT_FL0.ami and I2Cn_INT_FL0.txloi.
3. SW waits for I2Cn_INT_FL0.ami =1, either via polling the interrupt flag or setting I2Cn_INT_EN0.amie to interrupt
the CPU.
4. After reading I2Cn_INT_FL0.ami =1, SW reads I2Cn_CTRL0.read to determine whether the transaction is a transmit
(read=1) or receive (read=0) operation. In this case we assume read=1, indicating transmit.
a. At this point, HW will hold SCL low until SW clears I2Cn_INT_FL0.txloi and loads data into the FIFO.
5. SW clears I2Cn_INT_FL0.ami and I2Cn_INT_FL0.txloi. Now that I2Cn_INT_FL0.txloi is 0, SW can begin loading the
transmit data into I2Cn_FIFO.
6. As soon as there is data in the FIFO, HW will release SCL (after counting out I2Cn_CLK_HI.scl_hi) and send out the
data on the bus.
7. While the master keeps requesting data and sending ACKs, I2Cn_INT_FL0.donei will remain 0 and SW should
continue to monitor the TX FIFO and refill it as needed.
a. The FIFO level can be monitored synchronously via the TX FIFO status/interrupt flags, or asynchronously by
setting I2Cn_TX_CTRL0.txth and setting I2Cn_INT_EN0.txthie interrupt.
b. If the TX FIFO ever empties during the transaction, the HW will start clock stretching and wait for it to be
refilled.
8. The master ends the transaction by sending a NACK. Once this happens the I2Cn_INT_FL0.donei interrupt flag is
set, and SW can stop monitoring the TX FIFO.
9. The transaction is complete, SW should "clean up", including clearing I2Cn_INT_FL0.donei and clearing
I2Cn_INT_EN0.txthie interrupt. We return to step 3, waiting on an address match.
10. If SW needs to know how many data bytes were transmitted to the master, it should check the TX FIFO level as
soon as SW sees I2Cn_INT_FL0.donei = 1 and use that to determine how many data bytes were successfully sent.
a. Please note that any data remaining in the TX FIFO will be discarded prior to the next transmit operation; it is
NOT necessary for SW to manually flush the TX FIFO for this to occur.
The other mode of operation for slave transmit is preload mode. In this mode, it is assumed that the application firmware
knows prior to the transmit operation what data it should send to the master. This data is then “preloaded” into the TX
FIFO. Once the address match occurs, this data can be sent out without any software intervention. Preload mode can be
used with clock stretching either enabled or disabled, but it is the only option if clock stretching must be disabled.
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