Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 385 of 457
Watchdog Timer Control Register
WDTn_CTRL
[0x0000]
Bits
Name
Access
Reset
Description
7:4
rst_period
R/W
0
WDT Reset Period
Sets the number of PCLK cycles until a system reset occurs if the watchdog timer
is not reset. This field is set to 0 on a POR and is not affected by other resets.
0xF: 

 

0xE: 

 

0xD: 

 

0xC: 

 

0xB: 

 

0xA: 

 

0x9: 

 

0x8: 

 

0x7: 

 

0x6: 

 

0x5: 

 

0x4: 

 

0x3: 

 

0x2: 

 

0x1: 

 

0x0: 

 

3:0
int_period
R/W
0
WDT Interrupt Period
Sets the number of PCLK cycles until a watchdog timer interrupt is generated.
This field is set to 0 on a POR and is not affected by other resets.
0xF: 

 

0xE: 

 

0xD: 

 

0xC: 

 

0xB: 

 

0xA: 

 

0x9: 

 

0x8: 

 

0x7: 

 

0x6: 

 

0x5: 

 

0x4: 

 

0x3: 

 

0x2: 

 

0x1: 

 

0x0: 

 


Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English