Maxim Integrated MAX32665 User Manual

MAX32665-MAX32668 User Guide
Maxim Integrated Page 445 of 457
Cryptographic Control Register
CRYPTO_CTRL
[0x0000]
BITS
NAME
ACCESS
RESET
DESCRIPTION
29
err
R
0
AHB Bus Error
This bit is set if the DMA attempts to access non-existent or protected memory on the
AHB bus. This bit can only be cleared by resetting the cryptographic accelerator block.
0: No error
1: Cryptographic accelerator DMA bus error
28
maa_done
R/W
0
MAA Operation Done
Clear this bit before starting a new MAA operation. This bit is read only while the MAA
is in progress. This bit is the opposite of MAA_CTRL.stc.
0: MAA operation in progress
1: Last MAA operation done
27
cph_done
R/W
0
Cipher Done
This bit is set when a block cipher encryption/decryption operation is complete. Clear
this bit before starting a cipher operation.
0: Not done
1: Last cipher operation done
26
hsh_done
R/W
0
Hash Done
This bit is set to 1 when they cryptographic accelerator has completed a SHA
operation is complete. Clear this bit before starting the next hash operation.
0: Not done
1: SHA/hash operation done
25
gls_done
R/W
0
Galois Done
FIFO is full, and CRC or the Hamming Code Generator is enabled. Clear this bit before
starting a CRC operation.
0: Not done
1: Operation done
24
dma_done
R/W
0
DMA Done
DMA write/read operation is complete. Clear this bit before starting a DMA operation.
0: Not done
1: Operation done
23:16
-
RO
0
Reserved for Future Use
Do not modify this field from its default value.
15
dmadnemsk
R/W
0
DMA Done Flag Mask
This field prevents the CRYPTO_CTRL.dma_done flag from setting the
CRYPTO_CTRL.done flag. The CRYPTO_CTRL.dma_done flag will still be set.
0: CRYPTO_CTRL.dma_done flag will not set CRYPTO_CTRL.done
1: CRYPTO_CTRL.dma_done flag will also set CRYPTO_CTRL.done
14
flag_mode
R/W
0
Done Flag Mode
This bit provides legacy support for the access behavior of the done flags. It should
not be changed from its default value.
0: (Default) Unrestricted write(0 or 1) of CRYPTO_CTRL[27:24]
1: Access to CRYPTO_CTRL[27:24] is “write 1 to clear/write 0 no effect”
13:12
-
RO
0
Reserved for Future Use
Do not modify this field from its default value.
11:10
rdsrc
R/W
0
Read FIFO Source Select
This field selects the source of the read FIFO data.
0b00: DMA disabled
0b01: DMA or APB
0b10: RNG
0b11: Reserved

Maxim Integrated MAX32665 Specifications

General

Brand	Maxim Integrated
Model	MAX32665
Category	Motherboard
Language	English