Maxim Integrated MAX32665 - Page 204

MAX32665-MAX32668 User Guide
Maxim Integrated Page 204 of 457
Normal Interrupt Status Register
SDHC_INT_STAT
[0x0030]
Bits
Name
Access
Reset
Description
5
buff_rd_ready
RW1C
0
Buffer Read Ready
Set if the Buffer Read Enable field in the Present State register
(SDHC_PRESENT.buff_rd_ready) changes from 0 to 1.
1: Ready to read buffer
0: Not ready to read buffer
Note: This field is set to 1 for every CMD19 execution while performing a tuning
procedure (SDHC_HOST_CN_2.execute = 1).
4
buff_wr_ready
RW1C
0
Buffer Write Ready
Set if the Buffer Write Enable field in the Present State register
(SDHC_PRESENT.buff_wr_ready) changes from 0 to 1.
1: Ready to write buffer
0: Not ready to write buffer
3
dma
RW1C
0
DMA Interrupt
Set when the SDHC encounters the DMA buffer boundary set in the
SDHC_BLK_SIZE.trans field during a SDMA transfer. The Card Driver must update the
SDHC_SDMA register with the address of the next block to transfer before the SDHC
continues the transfer.
1: SDHC DMA Interrupt is generated
0: No SDHC DMA Interrupt
2
blk_gap_event
RW1C
0
Block Gap Event
If the Stop at Block Gap Request field is set in the Block Gap Control register
(SDHC_BLK_GAP.stop), this bit is set when a read or write transaction is stopped at a
block gap. If Stop at Block Gap Request is not set to 1, then this bit is not
meaningless.
1: Transaction stopped at block gap
0: No Block Gap Event
1
trans_comp
RW1C
0
Transfer Complete
Set when a read/write transfer and a command with busy is complete. This bit has
higher priority than Data Timeout Error. If both bits are set to 1, execution of a
command is complete. See Table 8-74 for Transfer Complete and Data Timeout Error
priority and meaning.
1: Command execution is complete
0: Not complete
Note: This field is not set while performing a tuning procedure
(SDHC_HOST_CN_2.execute = 1).
0
cmd_cmp
RW1C
0
Command Complete
Set when the end bit of the command response is received. Auto CMD12 and Auto
CMD23 consist of two responses. This flag is not set by the card’s response to the
CMD12 or CMD23, but by the card’s response to the read or write command you
send to complete the Auto CMD12 or Auto CMD23. See Command Inhibit (CMD) in
the Present State (SDHC_PRESENT.cmd_comp) register for how to control this bit.
Table 8-75 illustrates the relationship between Command Complete and Command
Timeout Error bits. If both bits are set, then the response was not received within 64
SD clock cycles.
1: Command execution is complete
0: Not complete