Maxim Integrated MAX32665 - Page 13

MAX32665-MAX32668 User Guide
Maxim Integrated Page 13 of 457
23.9 Register Details ------------------------------------------------------------------------------------------------------------ 444
24. Revision History ---------------------------------------------------------------------------------------------------- 457
List of Figures
Figure 1-1: MAX32665—MAX32668 Block Diagram .................................................................................................................. 25
Figure 3-1: Code Memory Mapping ........................................................................................................................................... 35
Figure 3-2: Data Memory Mapping ........................................................................................................................................... 36
Figure 4-1: Clock Block Diagram ................................................................................................................................................ 51
Figure 4-2: Example 32MHz Crystal Capacitor Determination .................................................................................................. 53
Figure 4-3: SLEEP Mode Clock Control ....................................................................................................................................... 55
Figure 4-4: DEEPSLEEP Clock Control ......................................................................................................................................... 57
Figure 4-5: BACKUP Mode Clock Control ................................................................................................................................... 59
Figure 4-6: MAX32665—MAX32668 Cache Controllers Control ............................................................................................... 63
Figure 8-1. Simplified SPIXF Block Diagram ............................................................................................................................. 143
Figure 8-2. Simplified Block Diagram ....................................................................................................................................... 144
Figure 8-3. SPIXFC Transaction Delay ...................................................................................................................................... 149
Figure 8-4. Supported SPI configuration .................................................................................................................................. 159
Figure 8-5. SPIXFM Delay Configuration .................................................................................................................................. 160
Figure 8-6. Simplified SPIXR Block Diagram ............................................................................................................................. 168
Figure 8-7: SDHC Block Diagram .............................................................................................................................................. 182
Figure 8-8: SD Bus Protocol - No Response and No Data Operations ...................................................................................... 183
Figure 8-9: SD Bus Protocol - Multi-Block Read Operation ...................................................................................................... 184
Figure 8-10: SD Bus Protocol - Multi Block Write Operation ................................................................................................... 184
Figure 9-1: DMA Block-Chaining Flowchart ............................................................................................................................. 229
Figure 10-1: Galois Field CRC and LFSR Architecture ............................................................................................................... 240
Figure 11-1: Analog to Digital Converter Block Diagram ......................................................................................................... 248
Figure 11-2: ADC Limit Engine ................................................................................................................................................. 253
Figure 12-1: UART Frame Diagram .......................................................................................................................................... 260
Figure 13-1: I
2
C Block Diagram................................................................................................................................................. 273
Figure 13-2: I
2
C Write Data Transfer ........................................................................................................................................ 276
Figure 13-3: I
2
C SCL Timing for Standard, Fast, and Fast-Plus Modes ..................................................................................... 278
Figure 14-1: QSPI Block Diagram ............................................................................................................................................. 307
Figure 14-2: 4-Wire SPI Connection Diagram .......................................................................................................................... 309
Figure 14-3: Generic 3-Wire SPI Master to Slave Connection ................................................................................................. 310
Figure 14-4: Dual Mode SPI Connection Diagram .................................................................................................................... 311
Figure 14-5: SCK Clock Rate Control ........................................................................................................................................ 312
Figure 14-6: SPI Clock Polarity ................................................................................................................................................. 313
Figure 16-1: One-Shot Mode Diagram ..................................................................................................................................... 330
Figure 16-2: Continuous Mode Diagram .................................................................................................................................. 332
Figure 16-3: Counter Mode Diagram ....................................................................................................................................... 334
Figure 16-4: Capture Mode Diagram ....................................................................................................................................... 338
Figure 16-5: Counter Mode Diagram ....................................................................................................................................... 340
Figure 16-6: Gated Mode Diagram .......................................................................................................................................... 342
Figure 18-1. MAX32665―MAX32668 RTC Block Diagram (12-bit Sub-Second Counter) ........................................................ 369
Figure 18-2. RTC Busy/Ready Signal Timing ............................................................................................................................. 371
Figure 18-3. RTC Interrupt/Wakeup Diagram Wakeup Function ............................................................................................. 373
Figure 18-4. Internal Implementation of Digital Trim, 4kHz .................................................................................................... 375
Figure 19-1: Watchdog Timer Block Diagram .......................................................................................................................... 381
Figure 20-1: 1-Wire Signal Interface ........................................................................................................................................ 389