MAX32665-MAX32668 User Guide
Maxim Integrated Page 3 of 457
3.4.1 Core AHB Interfaces --------------------------------------------------------------------------------------------------------------------- 40
3.4.2 AHB Masters ------------------------------------------------------------------------------------------------------------------------------ 41
3.5 Peripheral Register Map --------------------------------------------------------------------------------------------------- 41
3.5.1 APB Peripheral Base Address Map -------------------------------------------------------------------------------------------------- 41
3.5.2 AHB Peripheral Base Address Map ------------------------------------------------------------------------------------------------- 42
3.6 Error Correction Coding (ECC) Module --------------------------------------------------------------------------------- 43
3.6.1 SRAM --------------------------------------------------------------------------------------------------------------------------------------- 43
3.6.2 FLASH --------------------------------------------------------------------------------------------------------------------------------------- 43
3.6.3 Cache --------------------------------------------------------------------------------------------------------------------------------------- 43
3.6.4 Limitations--------------------------------------------------------------------------------------------------------------------------------- 43
4. System, Power, Clocks, Reset --------------------------------------------------------------------------------------- 50
4.1 Oscillator Sources and Clock Switching -------------------------------------------------------------------------------- 50
4.1.1 Oscillator Inplementation ------------------------------------------------------------------------------------------------------------- 52
4.1.2 96MHz Internal Main High-Speed Oscillator ------------------------------------------------------------------------------------- 52
4.1.3 60MHz Low Power Internal Oscillator --------------------------------------------------------------------------------------------- 52
4.1.4 32MHz Bluetooth Radio Oscillator -------------------------------------------------------------------------------------------------- 52
4.1.5 7.3728MHz Internal Oscillator ------------------------------------------------------------------------------------------------------- 53
4.1.6 32.768kHz External Crystal Oscillator ---------------------------------------------------------------------------------------------- 53
4.1.7 8kHz Ultra-Low Power Nano-Ring Internal Oscillator ------------------------------------------------------------------------- 53
4.2 Operating Modes ------------------------------------------------------------------------------------------------------------ 54
4.2.1 ACTIVE Mode ----------------------------------------------------------------------------------------------------------------------------- 54
4.2.2 SLEEP Low Power Mode --------------------------------------------------------------------------------------------------------------- 54
4.2.3 DEEPSLEEP Low Power Mode -------------------------------------------------------------------------------------------------------- 56
4.2.4 BACKUP Low Power Mode ------------------------------------------------------------------------------------------------------------ 58
4.3 Device Resets ----------------------------------------------------------------------------------------------------------------- 60
4.3.1 Peripheral Reset ------------------------------------------------------------------------------------------------------------------------- 61
4.3.2 Soft Reset ---------------------------------------------------------------------------------------------------------------------------------- 61
4.3.3 System Reset ------------------------------------------------------------------------------------------------------------------------------ 62
4.3.4 Power-On Reset -------------------------------------------------------------------------------------------------------------------------- 62
4.4 Cache --------------------------------------------------------------------------------------------------------------------------- 62
4.5 Instruction Cache Controller ---------------------------------------------------------------------------------------------- 63
4.5.1 Enabling ICC0/ICC1/SFCC -------------------------------------------------------------------------------------------------------------- 63
4.5.2 Flushing the ICC0/ICC1/SFCC Cache ------------------------------------------------------------------------------------------------ 64
4.5.3 Flushing SRCC Cache -------------------------------------------------------------------------------------------------------------------- 64
4.6 Instruction Cache Controller Registers --------------------------------------------------------------------------------- 64
4.7 External RAM SPIXR Cache Controller (SRCC) ------------------------------------------------------------------------ 66
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