Maxim Integrated MAX32665 - Page 378

MAX32665-MAX32668 User Guide
Maxim Integrated Page 378 of 457
RTC Control Register
RTC_CTRL
[0x0010]
Bits
Field
Access
Reset
Description
7
ssec_alarm_fl
R/W
0*
Sub-second Alarm Interrupt Flag
This interrupt flag is set when a sub-second alarm condition occurs. This flag is a wake-
up source for the processor.
0: No sub-second alarm pending.
1: Sub-second interrupt pending.
*Note: Reset on POR only.
6
tod_alarm_fl
R/W
0*
Time-of-Day Alarm Interrupt Flag
This interrupt flag is set by hardware when a time-of-day alarm occurs.
0: No Time-of-Day alarm interrupt pending.
1: Time-of-day interrupt pending.
*Note: Reset on POR only.
5
ready_int_en
R/W
0*
RTC Ready Interrupt Enable
0: Disabled.
1: Enabled.
*Note: Reset on POR only.
4
ready
R/W0O
0*
RTC Ready
This bit is cleared to 0 by hardware during a hardware update of the RTC_SEC and
RTC_SSEC registers. Software should not read RTC_SEC and RTC_SSEC until hardware
sets the bit to 1 again. Software can clear this bit at any time. An RTC interrupt will be
generated if RTC_CTRL.ready_int_en = 1.
0: Software reads of RTC_SEC and RTC_SSEC invalid.
1: Software reads of RTC_SEC and RTC_SSEC valid.
*Note: Reset on POR only.
3
busy
RO
0*
RTC Busy Flag
This bit is set to 1 by hardware to indicate a register update is in progress when
software writes to:
• RTC_SEC register
• RTC_SSEC register
• RTC_TRIM register
• RTC_CTRL.enable
• RTC_CTRL.tod_alarm_en
• RTC_CTRL.ssec_alarm_en
The field is automatically cleared by hardware when the update is complete. Software
should poll this field for 0 after changing RTC registers before making any other RTC
register changes.
0: RTC not busy.
1: RTC busy.
*Note: Reset on POR only.
2
ssec_alarm_en
R/W
0*
Sub-Second Alarm Interrupt Enable
Check the RTC_CTRL.busy flag after writing to this field to determine when the RTC
synchronization is complete.
0: Disable.
1: Enable.
*Note: Reset on POR only.