Maxim Integrated MAX32665 - Page 99

MAX32665-MAX32668 User Guide
Maxim Integrated Page 99 of 457
Memory Zeroization Control
GCR_MEM_ZERO
[0x002C]
Bits
Field
Access
Reset
Description
13
usbfifoz
R/W
0
USB FIFO Zeroization
Write 1 to initiate the operation
0: Operation complete.
1: Operation in progress.
12
cryptoz
R/W
0
Crypto MAA Memory Zeroization
Write 1 to initiate the operation.
0: Operation complete.
1: Operation in progress.
11
scachetagz
R/W
0
SRCC Cache Tag Zeroization
Write 1 to clear the SRCC tag RAM.
0: Operation complete.
1: Operation in progress.
10
scachedataz
R/W
0
SRCC Cache Data Zeroization
Write 1 to initiate the operation to clear the SFCC Data RAM to 0.
0: Operation complete.
1: Operation in progress.
9
icachexipz
R/W
0
SFCC Cache Data and Tag Zeroization
Write 1 to clear the ICC1 16KB cache RAM to 0. The bit is set to 0 when the
operation is complete.
0: Operation complete.
1: Operation in progress.
8
icache0z
R/W
0
CPU0 ICC0 Cache Data and Tag Zeroization
Write 1 to initiate the operation.
0: Operation complete.
1: Operation in progress.
7
-
R/W
0
Reserved
Do not modify this field.
6
sram6z
R/W
0
Sysram6 to Sysram11 Zeroization
Write 1 to initiate the operation.
0: Operation complete.
1: Operation in progress.
5
sram5z
R/W
0
Sysram5 Zeroization
Write 1 to initiate the operation.
0: Operation complete.
1: Operation in progress.
4
sram4z
R/W
0
Sysram4 Zeroization
Write 1 to initiate the operation.
0: Operation complete.
1: Operation in progress.
3
sram3z
R/W
0
Sysram3 Zeroization
Write 1 to initiate the operation.
0: Operation complete.
1: Operation in progress.
2
sram2
R/W1
0
Sysram2 Zeroization
Write 1 to initiate the operation.
0: Operation complete.
1: Operation in progress.