Maxim Integrated MAX32665 - Page 15

MAX32665-MAX32668 User Guide
Maxim Integrated Page 15 of 457
List of Tables
Table 2-1: Dual Mapped APB Peripherals .................................................................................................................................. 26
Table 2-2. MAX32665—MAX32668 Master Permission Bits ..................................................................................................... 26
Table 2-3: MAX32665—MAX32668 AHB Slaves ........................................................................................................................ 27
Table 2-4. MAX32665—MAX32668 AHB Master/Slave Interconnect Matrix ............................................................................ 27
Table 2-5: RPU APB Register Offsets, Names, Access, and Descriptions ................................................................................... 29
Table 2-6: RPU AHB Slave Register Addresses, Names, Access, and Descriptions .................................................................... 30
Table 2-7: RPU APB Slave Permission Registers ......................................................................................................................... 31
Table 2-8: RPU AHB Slave Permission Register .......................................................................................................................... 33
Table 3-1: APB Peripheral Base Address Map............................................................................................................................ 41
Table 3-2: AHB Peripheral Base Address Map ........................................................................................................................... 43
Table 3-3: Error Correction Coding (ECC) Enable Register ......................................................................................................... 44
Table 3-4: Error Correction Coding (ECC) Error Register ........................................................................................................... 44
Table 3-5: Correctable Error Detected Register ......................................................................................................................... 46
Table 3-6: Error Correction Coding (ECC) Interrupt Enable Register ......................................................................................... 47
Table 3-7: Error Correction Coding (ECC) Address Register ....................................................................................................... 48
Table 4-1: Wakeup Sources ....................................................................................................................................................... 54
Table 4-2: Reset and Low Power Mode Effects ......................................................................................................................... 61
Table 4-3: Instruction Cache Controller Register Summary ....................................................................................................... 64
Table 4-4: SPIXF Cache Controller Register Summary ............................................................................................................... 64
Table 4-5: ICCn Cache ID Register .............................................................................................................................................. 64
Table 4-6: ICCn Memory Size Register ....................................................................................................................................... 65
Table 4-7: ICCn Cache Control Register ..................................................................................................................................... 65
Table 4-8: ICCn Invalidate Register ............................................................................................................................................ 65
Table 4-9: SFCC Cache ID Register ............................................................................................................................................. 65
Table 4-10: SFCC Memory Size Register .................................................................................................................................... 66
Table 4-11: SFCC Cache Control Register ................................................................................................................................... 66
Table 4-12: SFCC Invalidate Register ......................................................................................................................................... 66
Table 4-13 RAM Block Size and Base Address ........................................................................................................................... 67
Table 4-14 Miscellaneous Control Register Summary ............................................................................................................... 68
Table 4-15: Error Correction Coding (ECC) Enable Register ....................................................................................................... 68
Table 4-16: SQWOUT and PDOWN Output Enable Register ...................................................................................................... 69
Table 4-17: Comparator Enable Register ................................................................................................................................... 69
Table 4-18: Control Register ...................................................................................................................................................... 70
Table 4-19: SIMO Power Supply Device Pin Connectivity .......................................................................................................... 71
Table 4-20: SIMO Controller Register Summary ........................................................................................................................ 72
Table 4-21: Buck Voltage Regulator A Control Register ............................................................................................................ 73
Table 4-22: Buck Voltage Regulator B Control Register ............................................................................................................. 73
Table 4-23: Buck Voltage Regulator C Control Register ............................................................................................................. 74
Table 4-24: Buck Voltage Regulator D Control Register ............................................................................................................ 74
Table 4-25: High Side FET Peak Current VREGO_A VREGO_B Register...................................................................................... 74
Table 4-26: High Side FET Peak Current VREGO_C VREGO_D Register ..................................................................................... 75
Table 4-27: Maximum High Side FET Time On Register ............................................................................................................. 75
Table 4-28: Buck Cycle Count VREGO_A Register ...................................................................................................................... 75
Table 4-29: Buck Cycle Count VREGO_B Register ...................................................................................................................... 75
Table 4-30: Buck Cycle Count VREGO_C Register ...................................................................................................................... 76
Table 4-31: Buck Cycle Count VREGO_D Register ...................................................................................................................... 76
Table 4-32: Buck Cycle Count Alert VREGO_A Register ............................................................................................................. 76
Table 4-33: Buck Cycle Count Alert VREGO_B Register ............................................................................................................. 76
Table 4-34: Buck Cycle Count Alert VREGO_C Register ............................................................................................................. 76
Table 4-35: Buck Cycle Count Alert VREGO_D Register ............................................................................................................. 77